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STM32F407F4 Discovery: USART Master-Slave Communication Issue

Mohammed_sanaulla
Associate

I’m trying to establish USART communication between two STM32F407-Discovery boards, where one board acts as Master and the other as Slave.

Hardware setup
Master Board clk -> save board Clk  - [common clock]
Master Board TX → Slave Board RX
Master Board RX ← Slave Board TX
Both GND connected
Using STM32F407-Discovery boards
  
SYNCHRONOUS MODE

connectivity configurations

  • USART port used (e.g., USART2)

  • Baud rate (e.g., 115200)

  • Word length (8 bits)

  • Parity (None)

  • Stop bits (1)

  • Clock settings ( synchronous) 
    clock polarity : low
    clock phase : one edge

    code of master and slave:

    // Master
    char data = 'A';
    HAL_USART_Transmit(&huart2, (uint8_t*)&data, 1, HAL_MAX_DELAY);

    // Slave
    char rx;
    HAL_USART_Receive(&huart2, (uint8_t*)&rx, 1, HAL_MAX_DELAY);

    output : Im getting grbage value like 127@ , so on

    What I've tried 
    - Verified TX/RX wiring
    - Checked baud rate matching
    - Tried loopback test on each board (TX→RX)
    - Switched from polling to interrupt-based reception



 

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