How to prevent unaligned access on backup ram?

[OliM]

(and why is this a problem?)

It looks like the backup ram can not be called through unaligned access on my STM32U585. The mighty internet says that this should not be completely unexpected since it is basically a peripheral and no standard Ram.

I have set up the BKPSRAM in the linker file like this:

#include "partition.h"

/* Entry Point */
ENTRY(Reset_Handler)

/* Highest address of the user mode stack */
_estack = ORIGIN(RAM) + LENGTH(RAM);	/* end of "RAM" Ram type memory */

_Min_Heap_Size = 0x000 ;	/* required amount of heap  */
_Min_Stack_Size = 0x800 ;	/* required amount of stack */

/* Memories definition */
MEMORY
{
  BKPSRAM (xrw)	: ORIGIN = 0x40036400,	LENGTH = 2K
  SRAM4	(xrw)	: ORIGIN = 0x28000000,	LENGTH = 16K
  RAM	(xrw)	: ORIGIN = 0x20000000,	LENGTH = NON_SEC_RAM_SIZE    /*  Secure is using end RAM3 (64k). Actual start is 0x20000000 and actual length is 768K */
  FLASH	(rx)	: ORIGIN = 0x8000000 + APP_SLOT0_NON_SEC_APP_OFFSET,	LENGTH = NON_SEC_APP_SIZE   /* Memory is divided. Actual start is 0x08000000 and actual length is 2048K */
}
/* Sections */
SECTIONS
{
...
  /* backup ram area */
  BKUP_RAM(NOLOAD):
  {
    . = ALIGN(8);
    *(BKUP_RAM)
    *(BKUP_RAM*)
    . = ALIGN(8);
  }>BKPSRAM
...

The respective variables are moved in the section BKUP_RAM accordingly.

Compiler is the arm GCC toolchain 14.2.

I have found out that I can solve this with -mno-unaligned-access for the complete project, but of course this means missed optimization through the whole project. Is there a way to only mark the specific section/variables instead?

[OliM]

Ok, so to reiterate:

• M33 (and older devices as well?) always has an active MMU (!)
  • MPU disabled means MMU is running with default memory map
• The default memory region in STM32U5 defines the complete 0x40000000 - 0x60000000 region as peripherals and therefore device memory 
• BKPSRAM is inside the Peripheral Address range, so the default map puts it as device memory
• To use BKPSRAM as "normal" memory, the MPU needs to be enabled and its region defined specifically

Is this the gist of it?

In code I now use the following and that seems to solve my issue:

static void initMpu(void)
{
    // 1. Select MPU Region Number
    MPU_NS->RNR = 0;
    //2. define an attribute type which matches normal memory
    MPU_NS->MAIR0 = 0x00000033;
    // 3. Set Base Address, Access Permissions (Read/Write)
    MPU_NS->RBAR = (0x40036400 & MPU_RBAR_BASE_Msk) |
                (0x01UL << MPU_RBAR_AP_Pos);// Read/Write for Privileged and Unprivileged

    // 4. Set Limit Address, Link to Attribute 0 (ATTR0), and Enable Region
    MPU_NS->RLAR = ((0x40036400 + 0x800 -1)  & MPU_RLAR_LIMIT_Msk) |
                (0x0UL << MPU_RLAR_AttrIndx_Pos)  | // Link to ATTR0 (Normal memory)
                (0x1UL << MPU_RLAR_EN_Pos);         // Enable this MPU region
    //5. enable the MPU, keeping the default map in the background
    MPU_NS->CTRL |= (0x1UL << MPU_CTRL_ENABLE_Pos) | (1UL << MPU_CTRL_PRIVDEFENA_Pos);
}

[mƎALLEm · Accepted solution]

Hello,

---

@OliM wrote:

• M33 (and older devices as well?) always has an active MMU (!)

---

If you are referring MMU to the Memory Management Unit: there is no MMU on Cortex-M. 

---

@OliM wrote:

• The default memory region in STM32U5 defines the complete 0x40000000 - 0x60000000 region as peripherals and therefore device memory 
• BKPSRAM is inside the Peripheral Address range, so the default map puts it as device memory
• To use BKPSRAM as "normal" memory, the MPU needs to be enabled and its region defined specifically

---

Indeed.

According to the reference manual, BKPSRAM is in the range of:

and according to the programming manual PM0264, Backup SRAM is in the Peripheral memory range address which has a memory attribute: Device:

As said by @waclawek.jan , and according to the CM33 TRM:

https://developer.arm.com/documentation/100230/0100/Programmers-Model/Memory-model/Unaligned-accesses:

So you need to use MPU and configure BKPSRAM memory region of 2K as Normal memory attribute.