Dear Sir /Mam
We are currently working with LPDDR4 (MT53E512M32D1ZW-046 WT:B) on our platform. To validate our setup, we used the DDR firmware code available at
STM32DDRFW-UTIL, which provides drivers for LPDDR4 (MT53E1GD2FW-046 WT:C).
During our testing on the STM32MP257F-DK board, the DDR tests pass successfully with the MT53E1GD2FW-046 WT:C configuration. However, when we run the same code with the MT53E512M32D1ZW-046 WT:B device, the PHY training fails.
We would like to clarify the following points:
Can the same DDR firmware and PHY training code be reused across both devices, given their differences in density and die configuration?
We are attaching the register initialisation file for DDRCTRL and DDRPHYC used in our setup(stm32mp2xx-lpddr4-1x32Gbits-1x32bits-template.h )and phy training is mentioned in stm32mp2xx_hal_ddr_ddrphy_firmware_ddr_pmu_train.c. Could you confirm what exactly is written into the PHY training phase?
The STM32MP25 reference manual states that the DDR initialisation sequence and training firmware are provided automatically through STM32CubeMX, based on user configuration inputs. However, after generating code via CubeMX, we only found the stm32mp25-mx.dts(We renamed the file while attaching as .dtsi is not supported) file containing register values, and no explicit DDR PHY training firmware was visible. Could you clarify where this firmware is located or how it is integrated?
System Setup Summary:
Board: STM32MP257F-DK (Rev. [please insert revision])
DDR Device:
Working: MT53E1GD2FW-046 WT:C (1Gb x32, 2-die)
Failing: MT53E512M32D1ZW-046 WT:B (512Mb x32, 1-die)
DDR Frequency: 1200 MHz
DDR Tool/Firmware: STM32DDRFW-UTIL from GitHub repository linked above
Test Outcome: Pass with MT53E1GD2FW, PHY training failure with MT53E512M32D1ZW
We would appreciate your guidance on resolving the PHY training failure for the MT53E512M32D1ZW-046 WT:B device, so that we can proceed with our development.
Thank you for your support.
