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STM32MP25 CubeMX Export Generates Invalid OP-TEE RIF DTS – Syntax Error in fip.dtsi / rif.dtsi During Build

jumman_JHINGA
Senior III

‎2025-11-14 4:21 AM

 

Hello,

I am working on an STM32MP257F platform using the STM32MPU OpenSTLinux Distribution (V25), together with the latest STM32CubeMX code-generation flow for the STM32MP257F-DK board.

I am using the STM32MPU-OSTL-DEV-helper to build the full BSP (Kernel + U-Boot + OP-TEE).
The Linux DTS and U-Boot DTS build correctly.
However, the OP-TEE Device Tree compilation fails with the following error:

Error: stm32mp257f-mydts-mx-rif.dtsi:63.116-117 syntax error
FATAL ERROR: Unable to parse input tree

 

To investigate, I inspected the CubeMX-generated OP-TEE RIF file:

STM32MPU-OSTL-DEV-helper/DEVICETREE/myDTS/optee/stm32mp257f-mydts-mx-rif.dtsi

Using:

nl -ba stm32mp257f-mydts-mx-rif.dtsi | sed -n '60,130p'



The file appears syntactically correct. For example:

60			RIFPROT(STM32MP25_RIFSC_I2C5_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    61			RIFPROT(STM32MP25_RIFSC_I2C6_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    62			RIFPROT(STM32MP25_RIFSC_I2C7_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    63			RIFPROT(STM32MP25_RIFSC_I2C8_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
    64			RIFPROT(STM32MP25_RIFSC_SAI1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    65			RIFPROT(STM32MP25_RIFSC_SAI2_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    66			RIFPROT(STM32MP25_RIFSC_SAI3_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    67			RIFPROT(STM32MP25_RIFSC_SAI4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    68			RIFPROT(STM32MP25_RIFSC_MDF1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    69			RIFPROT(STM32MP25_RIFSC_ADF1_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    70			RIFPROT(STM32MP25_RIFSC_FDCAN_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    71			RIFPROT(STM32MP25_RIFSC_HDP_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    72			RIFPROT(STM32MP25_RIFSC_ADC12_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    73			RIFPROT(STM32MP25_RIFSC_ADC3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
    74			RIFPROT(STM32MP25_RIFSC_ETH1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
    75			RIFPROT(STM32MP25_RIFSC_ETH2_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    76			RIFPROT(STM32MP25_RIFSC_ETHSW_DEIP_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    77			RIFPROT(STM32MP25_RIFSC_ETHSW_ACM_MSGBUF_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    78			RIFPROT(STM32MP25_RIFSC_ETHSW_ACM_CFG_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    79			RIFPROT(STM32MP25_RIFSC_USBH_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    80			RIFPROT(STM32MP25_RIFSC_USB3DR_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    81			RIFPROT(STM32MP25_RIFSC_COMBOPHY_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    82			RIFPROT(STM32MP25_RIFSC_PCIE_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
    83			RIFPROT(STM32MP25_RIFSC_UCPD1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
    84			RIFPROT(STM32MP25_RIFSC_STGEN_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    85			RIFPROT(STM32MP25_RIFSC_SDMMC1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    86			RIFPROT(STM32MP25_RIFSC_SDMMC2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    87			RIFPROT(STM32MP25_RIFSC_SDMMC3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    88			RIFPROT(STM32MP25_RIFSC_GPU_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    89			RIFPROT(STM32MP25_RIFSC_LTDC_CMN_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    90			RIFPROT(STM32MP25_RIFSC_LTDC_L1L2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    91			RIFPROT(STM32MP25_RIFSC_LTDC_L3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    92			RIFPROT(STM32MP25_RIFSC_LTDC_ROT_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    93			RIFPROT(STM32MP25_RIFSC_DSI_CMN_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    94			RIFPROT(STM32MP25_RIFSC_DSI_TRIG_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    95			RIFPROT(STM32MP25_RIFSC_DSI_RDFIFO_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    96			RIFPROT(STM32MP25_RIFSC_LVDS_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    97			RIFPROT(STM32MP25_RIFSC_CSI_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    98			RIFPROT(STM32MP25_RIFSC_DCMIPP_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
    99			RIFPROT(STM32MP25_RIFSC_DCMI_PSSI_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
   100			RIFPROT(STM32MP25_RIFSC_VDEC_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   101			RIFPROT(STM32MP25_RIFSC_VENC_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   102			RIFPROT(STM32MP25_RIFSC_RNG_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   103			RIFPROT(STM32MP25_RIFSC_PKA_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   104			RIFPROT(STM32MP25_RIFSC_SAES_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   105			RIFPROT(STM32MP25_RIFSC_HASH_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   106			RIFPROT(STM32MP25_RIFSC_CRYP1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   107			RIFPROT(STM32MP25_RIFSC_CRYP2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
   108			RIFPROT(STM32MP25_RIFSC_IWDG1_ID, RIF_UNUSED, RIF_LOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   109			RIFPROT(STM32MP25_RIFSC_IWDG2_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   110			RIFPROT(STM32MP25_RIFSC_IWDG3_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
   111			RIFPROT(STM32MP25_RIFSC_IWDG4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
   112			RIFPROT(STM32MP25_RIFSC_IWDG5_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
   113			RIFPROT(STM32MP25_RIFSC_WWDG1_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
   114			RIFPROT(STM32MP25_RIFSC_WWDG2_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
   115			RIFPROT(STM32MP25_RIFSC_VREFBUF_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   116			RIFPROT(STM32MP25_RIFSC_DTS_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   117			RIFPROT(STM32MP25_RIFSC_RAMCFG_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   118			RIFPROT(STM32MP25_RIFSC_CRC_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
   119			RIFPROT(STM32MP25_RIFSC_SERC_ID, RIF_UNUSED, RIF_UNLOCK, RIF_SEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   120			RIFPROT(STM32MP25_RIFSC_GICV2M_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_PRIV, RIF_CID1, RIF_SEM_DIS, RIF_CFEN)
   121			RIFPROT(STM32MP25_RIFSC_I3C1_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
   122			RIFPROT(STM32MP25_RIFSC_I3C2_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
   123			RIFPROT(STM32MP25_RIFSC_I3C3_ID, EMPTY_SEMWL, RIF_LOCK, RIF_NSEC, RIF_NPRIV, RIF_UNUSED, RIF_SEM_EN, RIF_CFEN)
   124			RIFPROT(STM32MP25_RIFSC_I3C4_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
   125			RIFPROT(STM32MP25_RIFSC_ICACHE_DCACHE_ID, RIF_UNUSED, RIF_UNLOCK, RIF_NSEC, RIF_NPRIV, RIF_CID2, RIF_SEM_DIS, RIF_CFEN)
   126		>;
   127	};
   128	
   129	&fmc {
   130		st,protreg = <

 

There are no missing semicolons, mismatched parentheses, or broken tokens.
The file also builds perfectly when used by the Linux DTS flow and when testing it with the standalone make dtbs outside OP-TEE.
Only OP-TEE rejects this file.

Current Situation

✔ Kernel DTS builds successfully
✔ U-Boot DTS builds successfully

✘ OP-TEE DTS fails because of stm32mp257f-mydts-mx-rif.dtsi
✔ External DTS (EXT_DTS_FOR_MY_STM32MP257F-DK) builds successfully

This makes me question whether:

• CubeMX generated incorrect OP-TEE RIF Device Tree content,

or

• I missed a configuration step when exporting or integrating the CubeMX DTS output.

 

I am attaching my CubeMX-generated DTS files for reference and would greatly appreciate guidance on how to resolve this issue.

Thank you.

 

myDTS.zip
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1 REPLY 1
GatienC
ST Employee

‎2025-11-14 5:58 AM

Hello @jumman_JHINGA,

Depending on the OSTL version that you use, the defines: STM32MP25_RIFSC_LTDC_L0L1_ID and STM32MP25_RIFSC_LTDC_L2_ID may be renamed to: STM32MP25_RIFSC_LTDC_L1L2_ID and STM32MP25_RIFSC_LTDC_L3_ID but that's probably not the issue there. It's only FYI.

On my side, I succeeded to compile your board with my latest branch, are you sure you are on a correct tag? I just fixed the board by including the SCMI dts config file. because of a missing label but that was not your trace either.

Regards,

Gatien

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