What are the steps needed to use QSPI (QUADSPI) to interface to an FPGA?

[GLaure]

Hello!

Board: STM32MP157F using STM32MP15-Ecosystem-v3.1.0

We are using SPI4 to interface and control a FPGA by a custom SPI protocol driver.

This works great!

To get faster data transfer the QSPI interface should be used. The FPGA will deliver data with up to 200MBit/s.

This is how we currently configured SPI4:

/* SPI */
&spi4 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&spi4_pins_b>;
	pinctrl-1 = <&spi4_sleep_pins_b>;
	cs-gpios = <&gpioe 11 0>;   /* PE11 : SPI4,NSS */
	status = "okay";
 
	dspi@0 {
		compatible = "dspi4";
		reg = <0>; /* CS #0 */
		spi-max-frequency = <4500000>;
	};
};

https://wiki.st.com/stm32mpu/wiki/QUADSPI_device_tree_configuration

only talks about memory and the MTD framework.

Can I use something like this to access QSPI by a custom SPI protocol driver?

This is completely untested and should only serve to show what I want to achieve:

/* QUADSPI */
&qspi {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
	pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
	cs-gpios = <&gpiof 6 0>;   /* PF6 : GPIO8,SPI5,NSS */
	status = "okay";
 
	dqspi@0 {
		compatible = "dqspi";
		reg = <0>; /* CS #0 */
		spi-max-frequency = <15000000>;
	};
};

Is it possible to access QSPI by using spidev driver and tools?

Thank you for your help!

Bye Gunther

[GLaure]

I am one step further.

Using this dts snippet, spidev will be loaded and /dev/spidev0.0 created.

&qspi {                                                    
       pinctrl-names = "default", "sleep";                    
       pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
       pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
       reg = <0x58003000 0x1000>,
             <0x70000000 0x4000000>;                          
       #address-cells = <1>;
       #size-cells = <0>;
       status = "okay";
 
 
		spidev@0 {
			compatible = "st,spidev";
			reg = <0>; /* CS #0 */
			spi-max-frequency = <4500000>;
		};
 
   };

But spidev-tool fails with this error:

./spidev_test -D /dev/spidev0.0 -v
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 kHz)
can't send spi message: Unknown error 524
Aborted (core dumped)

 I never experienced that with the other SPI interfaces.

[Kevin HUBER · Accepted solution]

Hello @GLaure​ ,

Usually, the users use the FMC to control an external component via FPGA.

ST also recommends to use the FMC for that. This is why you don't find information about the couple QSPI / FPGA.

On the wiki, you have an example of the control of a PHY connected to the FMC bus (it could also be a FPGA):

DT configuration of the external bus interface controller (board level)

To have the best performance, I recommend you to configure the buswidth to 16 bits as made in the wiki example:

st,fmc2-ebi-cs-buswidth = <16>;

Hope it helps,

Regards,

Kévin

[GLaure]

Thanks Kevin,

that did help. We will test the FMC interface.

Bye Gunther