Hi Everyone,
I'm trying to understand the NOR Flash boot sequence of stm32mp257f-ev1.
Im using generated FlashLayout_nor-sdcard_stm32mp257f-ev1-optee.tsv to flash the st-image-weston image.
I want to understand how exactly the boot sequence is started and how it reaches to the u-boot (normal-world boot).
I had a pre-work in understanding this boot sequence, I need a clarification on my understanding
The stm32mp2 boards follow arm trusted boot chain. That means TF-A and OPtee will be the FSBL and U-boot will be SSBL.
So during the power on cycle the ROM code initiates the OCTOSPI interface of the Processor in Legacy SPI (MOSI and MISO) mode at HSI/2 = 32MHz speed.
Then is loads the Initial DT + BL2(optee) to SRAM and initialise the CPU clock and DDR.
Once the CPU is initialised, based on the arm-firmware SPI_NOR and SPI_MEM framework and the boot_device.c configuration, the OCTO SPI is configured to QUADSPI in 1-1-4 (QREAD) mode at max speed (133MHz) speed and loads the remaining Boot Loaders to DDR, and after BL32 the processor enters the UBoot (normal world boot). (To be specific i'm using macronix mx66l5xx series.)
I followed these references to understand whatever i explained earlier, please clarify my understanding and exactly how all fits in the boot sequence.
1. NOR Boot - ROM Code WiKi Page
2. boot_device.c configuration file (arm-firmware : github)
3. spi_nor.h (github : arm-firmware)
4. spi_nor.c (github : arm-firmware)
And also please confirm that NOR will be only used for BOOT (That too only till coping the Bootloaders into DDR, after that NOR will not be used for any other operation after normal-world boot).
And please let me know where those boot_device.c configuration goes in the final image and what exactly is it used for and when does it execute.
