We are using the STM32MP157A device in our application. inter process communication between the both A7 processor with the bare metal programming .

[srikanth]

We are using the STM32MP157A device in our application. inter process communication between the both A7 processor with the bare metal programming we have doubt that how to select the both the cores independently . That is both the A7 processors. We referred the Reference manual .But we unable to get exactly.

[PatrickF]

Hi,

using Cortex-A7 SMP in bare-metal is probably a not so easy task.

I guess inter-processor communication within same cluster (i.e the 2 x Cortex-A7 in STM32MP15x) does not need specific HW outside what ARM provides natively.

The IPCC in the STM32MP15x is used for communication between Linux and Cortex-M4, but not within the cluster of the two Cortex-A7.

I think Linux kernel is probably using only shared memory (usually cached DDR), SEV/WFE instructions and GIC SGI interrupts.

Maybe it exist 3rd party company which provide bare-metal libraries or support for that.

ST does not provide any SW nor support for bare-metal on STM32MP15.

Regards.

[Genadi Zawidowski]

classical spin-locks and memory areas can help you?

For targeting interrupts GIC hardware provide CPU MASK parameters in some software and hardware interrupts.