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STM32MP157C U-Boot hangs after board information?

jhi
Senior

‎2022-10-03 02:09 AM

I'm using a custom board (it is not DK1 even tho it says on boot log) with STM32MP157AAC. The boot hangs on u-boot without proper error message. Where should I start to search the failure? 

NOTICE:  CPU: STM32MP157AAC Rev.Z
NOTICE:  Model: STMicroelectronics STM32MP157A-DK1 STM32CubeMX board - openstlinux-5.15-yocto-kirkstone-mp1-v22.06.15
WARNING: regulator_get_by_phandle: phandle 9 not found
WARNING: VDD unknown
INFO:    Reset reason (0x15):
INFO:      Power-on Reset (rst_por)
INFO:    FCONF: Reading TB_FW firmware configuration file from: 0x2ffe2000
INFO:    FCONF: Reading firmware configuration information for: stm32mp_io
INFO:    Using SDMMC
INFO:      Instance 1
INFO:    Boot used partition fsbl1
WARNING: regulator_get_by_phandle: phandle 12 not found
NOTICE:  BL2: v2.6-stm32mp1-r1.0(debug):v2.6-dirty
NOTICE:  BL2: Built : 13:14:26, Nov 23 2021
INFO:    BL2: Doing platform setup
INFO:    RAM: DDR3-1066/888 bin G 2x2Gb 533MHz v1.44
INFO:    Memory size = 0x20000000 (512 MB)
INFO:    BL2: Loading image id 31
INFO:    Loading image id=31 at address 0x2ffff000
INFO:    Image id=31 loaded: 0x2ffff000 - 0x2ffff226
INFO:    FCONF: Reading FW_CONFIG firmware configuration file from: 0x2ffff000
INFO:    FCONF: Reading firmware configuration information for: dyn_cfg
INFO:    FCONF: Reading firmware configuration information for: stm32mp1_firewall
INFO:    BL2: Loading image id 4
INFO:    Loading image id=4 at address 0x2ffc5000
INFO:    Image id=4 loaded: 0x2ffc5000 - 0x2ffd9820
INFO:    BL2: Skip loading image id 21
INFO:    BL2: Skip loading image id 22
INFO:    BL2: Loading image id 23
INFO:    Loading image id=23 at address 0xc0500000
INFO:    Image id=23 loaded: 0xc0500000 - 0xc0511570
INFO:    BL2: Loading image id 26
INFO:    Loading image id=26 at address 0x2ffc0000
INFO:    Image id=26 loaded: 0x2ffc0000 - 0x2ffc3869
INFO:    BL2: Loading image id 5
INFO:    Loading image id=5 at address 0xc0100000
INFO:    Image id=5 loaded: 0xc0100000 - 0xc01ece98
NOTICE:  BL2: Booting BL32
INFO:    Entry point address = 0x2ffc5000
INFO:    SPSR = 0x1d3
ERROR:   fixedregulator@3 can not set any flag
WARNING: fixed_regulator_register:81 failed to register fixedregulator@3
NOTICE:  SP_MIN: v2.6-stm32mp1-r1.0(debug):v2.6-dirty
NOTICE:  SP_MIN: Built : 13:14:26, Nov 23 2021
INFO:    ARM GICv2 driver initialized
INFO:    Set calibration timer to 60 sec
INFO:    stm32mp1 IWDG1 is secure
INFO:    ETZPC: CRYP1 (9) could be non secure
INFO:    SP_MIN: Initializing runtime services
INFO:    SP_MIN: Preparing exit to normal world
 
 
U-Boot 2021.10-stm32mp-r1 (Oct 04 2021 - 15:09:26 +0000)
 
CPU: STM32MP157AAC Rev.Z
Model: STMicroelectronics STM32MP157A-DK1 STM32CubeMX board - openstlinux-5.15-yocto-kirkstone-mp1-v22.06.15
Board: stm32mp1 in trusted mode (st,stm32mp157a-tc1-is-mx)
DRAM:  INFO:    CPU 0 IT Watchdog 2
INFO:    CPU : 0
INFO:    sp_usr   : 0x0
INFO:    lr_usr   : 0x0
INFO:    spsr_irq : 0x0
INFO:    sp_irq   : 0x0
INFO:    lr_irq   : 0x0
INFO:    spsr_fiq : 0x0
INFO:    sp_fiq   : 0x0
INFO:    lr_fiq   : 0x0
INFO:    spsr_svc : 0x0
INFO:    sp_svc   : 0xc007fe40
INFO:    lr_svc   : 0xc0144fcd
INFO:    spsr_abt : 0x200001d7
INFO:    sp_abt   : 0xbadc0de
INFO:    lr_abt   : 0xc010018c
INFO:    spsr_und : 0x0
INFO:    sp_und   : 0x0
INFO:    lr_und   : 0x0
INFO:    spsr_mon : 0x200001d7
INFO:    sp_mon : 0x2ffd9e40
INFO:    lr_mon : 0xc0100184
INFO:    scr : 0x225
INFO:    pmcr : 0x41072000
 

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13 REPLIES 13
PatrickD
ST Employee

‎2022-10-03 03:37 AM

Hello,

"DRAM:"

it the last trace before relocation

https://wiki.st.com/stm32mpu/wiki/U-Boot_overview#U-Boot_execution_sequence

To debug in first step you can activate trace in common/board_f.c

to check in which 'initcall' the U-Boot intialization is stucked and the WatchDog occur.

Patrick

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jhi
Senior

‎2022-10-03 08:05 AM

Using bitbake, is there any easier method to do testing (enabling debug) than making patches?

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PatrickD
ST Employee

‎2022-10-04 12:54 AM

by using yocto tool = devtool

https://wiki.st.com/stm32mpu/wiki/How_to_cross-compile_with_the_Distribution_Package#Modifying_the_U-Boot

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jhi
Senior

‎2022-10-04 03:44 AM

I'm not really sure what I should be seeing. No function names just addresses. I wonder where is the map file to be able to see which function was the last one.

U-Boot 2021.10-stm32mp-r1-00006-gd71a9f0b2f-dirty (Oct 04 2022 - 10:33:01 +0000)
 
initcall: c011b029
U-Boot code: C0100000 -> C01D1EB8  BSS: -> C01DE844
initcall: c011aef5
initcall: c011b19d
initcall: c0101f59
CPU: STM32MP157AAC Rev.Z
initcall: c011b811
Model: STMicroelectronics STM32MP157A STM32CubeMX board - openstlinux-5.15-yocto-kirkstone-mp1-v22.06.15
Board: stm32mp1 in trusted mode (st,stm32mp157a-tc1-is-mx)
initcall: c011b2cd
initcall: c011aef9
initcall: c011b18d
DRAM:  initcall: c0102365
INFO:    CPU 0 IT Watchdog 2

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jhi
Senior

‎2022-10-04 03:59 AM

I found the System.map and the last function seems to be dram_init (initcall: c0102365). Isn't the RAM already initialized in tf-a?

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jhi
Senior

‎2022-10-04 05:01 AM

So it will stop on arch/arm/mach-stm32mp/dram_init.c

int dram_init(void)

{

...

ret = uclass_get_device(UCLASS_RAM, 0, &dev);

...

}

Any ideas how to fix or debug this? It doesn't return from this function so no RAM init failed message.

The RAM I'm having is not the same as in DK, but as it is already configured in tf-a there aren't any dts/dtsi files for it in u-boot.

/* DDR type / Platform	DDR3/3L
 * freq		533MHz
 * width	32
 * datasheet	0  = MT41J128M16-187 / DDR3-1066 bin G
 * DDR density	8
 * timing mode	optimized
 * Scheduling/QoS options : type = 2
 * address mapping : RBC
 * Tc > + 85C : N
 */
 
#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x2Gb 533MHz v1.44"
#define DDR_MEM_SPEED 533000
#define DDR_MEM_SIZE 0x20000000
 
#define DDR_MSTR 0x00040401
#define DDR_MRCTRL0 0x00000010
#define DDR_MRCTRL1 0x00000000
#define DDR_DERATEEN 0x00000000
#define DDR_DERATEINT 0x00800000
#define DDR_PWRCTL 0x00000000
#define DDR_PWRTMG 0x00400010
#define DDR_HWLPCTL 0x00000000
#define DDR_RFSHCTL0 0x00210000
#define DDR_RFSHCTL3 0x00000000
#define DDR_RFSHTMG 0x0081008B
#define DDR_CRCPARCTL0 0x00000000
#define DDR_DRAMTMG0 0x121B2414
#define DDR_DRAMTMG1 0x000A041C
#define DDR_DRAMTMG2 0x0608090F
#define DDR_DRAMTMG3 0x0050400C
#define DDR_DRAMTMG4 0x08040608
#define DDR_DRAMTMG5 0x06060403
#define DDR_DRAMTMG6 0x02020002
#define DDR_DRAMTMG7 0x00000202
#define DDR_DRAMTMG8 0x00001005
#define DDR_DRAMTMG14 0x000000A0
#define DDR_ZQCTL0 0xC2000040
#define DDR_DFITMG0 0x02060105
#define DDR_DFITMG1 0x00000202
#define DDR_DFILPCFG0 0x07000000
#define DDR_DFIUPD0 0xC0400003
#define DDR_DFIUPD1 0x00000000
#define DDR_DFIUPD2 0x00000000
#define DDR_DFIPHYMSTR 0x00000000
#define DDR_ADDRMAP1 0x00080808
#define DDR_ADDRMAP2 0x00000000
#define DDR_ADDRMAP3 0x00000000
#define DDR_ADDRMAP4 0x00001F1F
#define DDR_ADDRMAP5 0x07070707
#define DDR_ADDRMAP6 0x0F070707
#define DDR_ADDRMAP9 0x00000000
#define DDR_ADDRMAP10 0x00000000
#define DDR_ADDRMAP11 0x00000000
#define DDR_ODTCFG 0x06000600
#define DDR_ODTMAP 0x00000001
#define DDR_SCHED 0x00000C01
#define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x01000001
#define DDR_PERFLPR1 0x08000200
#define DDR_PERFWR1 0x08000400
#define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000
#define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000010
#define DDR_PCFGR_0 0x00010000
#define DDR_PCFGW_0 0x00000000
#define DDR_PCFGQOS0_0 0x02100C03
#define DDR_PCFGQOS1_0 0x00800100
#define DDR_PCFGWQOS0_0 0x01100C03
#define DDR_PCFGWQOS1_0 0x01000200
#define DDR_PCFGR_1 0x00010000
#define DDR_PCFGW_1 0x00000000
#define DDR_PCFGQOS0_1 0x02100C03
#define DDR_PCFGQOS1_1 0x00800040
#define DDR_PCFGWQOS0_1 0x01100C03
#define DDR_PCFGWQOS1_1 0x01000200
#define DDR_PGCR 0x01442E02
#define DDR_PTR0 0x0022AA5B
#define DDR_PTR1 0x04841104
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200001F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
#define DDR_DTPR2 0x10023600
#define DDR_MR0 0x00000840
#define DDR_MR1 0x00000000
#define DDR_MR2 0x00000208
#define DDR_MR3 0x00000000
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x00000038
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000

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jhi
Senior

‎2022-10-04 10:27 AM

I did enable logging for all the files I could find which are used from the dram_init, but I just can't get any meaningful results/error messages. I did add some printfs and found out that it will stop in uclass_get_device_tail() -> device_probe(). It seems to be a devicetree problem? Where should I try to look?

Here is the latest try:

  • initcall: c0102365 = dram_init
  • mallocs are from lists
CPU: STM32MP157AAC Rev.Z
initcall: c011b869
Model: STMicroelectronics STM32MP157A STM32CubeMX board - openstlinux-5.15-yocto-kirkstone-mp1-v22.06.15
Board: stm32mp1 in trusted mode (st,stm32mp157a-tc1-is-mx)
initcall: c011b325
initcall: c011af51
initcall: c011b1e5
DRAM:  initcall: c0102365
size=40, ptr=f98, limit=80000: c0080f58
0
   - 0 'pin-controller@50002000'
   - found
size=20, ptr=fb8, limit=80000: c0080f98

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PatrickD
ST Employee

‎2022-10-05 12:27 AM

Hi

The DDR are initialized in TF-A, but some DDR CTRL registers are read to compute the DDR size in U-Boot.

This feature allow to have the same U-Boot binary / same device tree for several DDR configuration (size) on SoM using STM32MP15x.

The watchdog seens occur when this access are done in /drivers/ram/stm32mp1/stm32mp1_ram.c::stm32mp1_ddr_probe()

=> stm32mp1_ddr_size()

Shortcut => change in arch/arm/mach-stm32mp/dram_init.c to remove the DDR size detection:

int dram_init(void)

{

gd->ram_size = 0x40000000; /* hardcode your DDR size here */

return 0;

}

just to confirm if it the only blocking point.

Then you can check the root cause of the issue for freeze: DDRCTL AXI clock deactivated, NS access not allowed to register...

in particular can you check the NS access of the DDR register, configurated in OP-TEE / SPMIN

in OP-TEE = /core/arch/arm/plat-stm32mp1/shared_resources.c

static void set_etzpc_secure_configuration(void)

{

/* Some peripherals shall be secure */

config_lock_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW);

config_lock_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW);

config_lock_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ETZPC_DECPROT_NS_R_S_W);

config_lock_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ETZPC_DECPROT_NS_R_S_W);

....

in TF-A for SP-MIN = /plat/st/stm32mp1/stm32mp1_shared_resources.c

static void set_etzpc_secure_configuration(void)

{

/* Some system peripherals shall be secure */

etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW);

etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW);

etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID,

ETZPC_DECPROT_NS_R_S_W);

etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID,

ETZPC_DECPROT_NS_R_S_W);

...

in booth case DDRCTRL and DDRPHYC can be read by Non Secure = U-Boot

Regards

Patrick

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jhi
Senior

‎2022-10-05 07:07 AM

Thanks for the help. It seems to work with the dram_init trick. Now it would be nice to know why I have to do it. Here are my clock and ETZP settings:

&rcc {
	st,hsi-cal;
	st,csi-cal;
	st,cal-sec = <60>;
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MCU_PLL3P
		CLK_PLL12_HSE
		CLK_PLL3_HSE
		CLK_PLL4_HSE
		CLK_RTC_LSE
		CLK_MCO1_DISABLED
		CLK_MCO2_DISABLED
	>;
 
	st,clkdiv = <
		1 /*MPU*/
		0 /*AXI*/
		0 /*MCU*/
		1 /*APB1*/
		1 /*APB2*/
		1 /*APB3*/
		1 /*APB4*/
		2 /*APB5*/
		23 /*RTC*/
		0 /*MCO1*/
		0 /*MCO2*/
	>;
 
	st,pkcs = <
		CLK_CKPER_HSE
		CLK_FMC_ACLK
		CLK_QSPI_ACLK
		CLK_ETH_DISABLED
		CLK_SDMMC12_PLL4P
		CLK_DSI_DSIPLL
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_SPI2S1_PLL3Q
		CLK_SPI2S23_PLL3Q
		CLK_SPI45_HSI
		CLK_SPI6_HSI
		CLK_I2C46_HSI
		CLK_SDMMC3_PLL4P
		CLK_USBO_USBPHY
		CLK_ADC_CKPER
		CLK_CEC_LSE
		CLK_I2C12_HSI
		CLK_I2C35_HSI
		CLK_UART1_HSI
		CLK_UART24_HSI
		CLK_UART35_HSI
		CLK_UART6_HSI
		CLK_UART78_HSI
		CLK_SPDIF_PLL4P
		CLK_FDCAN_PLL4R
		CLK_SAI1_PLL3Q
		CLK_SAI2_PLL3Q
		CLK_SAI3_PLL3Q
		CLK_SAI4_PLL3Q
		CLK_RNG1_LSI
		CLK_RNG2_LSI
		CLK_LPTIM1_PCLK1
		CLK_LPTIM23_PCLK3
		CLK_LPTIM45_LSE
	>;
 
	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
	pll2: st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;
		cfg = <2 65 1 0 0 PQR(1,1,1)>;
		frac = <0x1400>;
	};
 
	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
	pll3: st,pll@2 {
		compatible = "st,stm32mp1-pll";
		reg = <2>;
		cfg = <1 33 1 16 36 PQR(1,1,1)>;
		frac = <0x1a04>;
	};
 
	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
	pll4: st,pll@3 {
		compatible = "st,stm32mp1-pll";
		reg = <3>;
		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
	};
};
&etzpc{
	status = "okay";
	st,decprot = <
	/*"NS_R S_W" peripherals*/
	DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
	DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
	/*"Non Secured" peripherals*/
	DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
	/*"Secured" peripherals*/
	DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
	/*"Mcu Isolation" peripherals*/
	DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
 	
};

I did also try with:

&etzpc {
	st,decprot = <
		DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
		DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_S_RW, DECPROT_LOCK)
		DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_S_RW, DECPROT_LOCK)
		DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_LOCK)
		DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_LOCK)
		DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_LOCK)
	>;
};

Or do I have to unlock STM32MP1_ETZPC_DDRCTRL_ID?

 There isn't such a function in tf-a SP-MIN : static void set_etzpc_secure_configuration(void).

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