I am currently working on a design based around the STM32MP157C (mounted in the Seeed SoM - STM32MP157C).
I am trying to connect to the M4 Core on the target but I cannot halt it. When I attempt to do it, the debugger can halt the A7 CPU0 but fails at stopping the A7 CPU1 (Error: timeout waiting for DSCR bit change).
The M4 is completely inaccessible.
When I try to access the cores from the OpenOCD telnet interface, I can list the targets and get the following output after issuing a reset halt command.
> reset halt
stlink_dap_op_connect(connect)
SWD DPIDR 0x6ba02477
Deferring arp_examine of STM32MP157CACx.cm4
Use arp_examine command to examine it manually!
Target not examined, will not halt after reset!
stlink_dap_op_connect(connect)
stlink_dap_op_connect(reconnect)
SWD DPIDR 0x6ba02477
SWD DPIDR 0x6ba02477
STM32MP157CACx.cpu0: ran after reset and before halt ...
STM32MP157CACx.cpu1: ran after reset and before halt ...
STM32MP157CACx.cm4: hardware has 6 breakpoints, 4 watchpoints
STM32MP157CACx.cpu0 rev 5, partnum c07, arch f, variant 0, implementor 41
target halted in Thumb state due to debug-request, current mode: Supervisor
cpsr: 0x800001f3 pc: 0x00010bbc
MMU: enabled, D-Cache: disabled, I-Cache: enabled
timed out while waiting for target halted
TARGET: STM32MP157CACx.cpu1 - Not halted
> targets
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0 STM32MP157CACx.ap1 mem_ap little STM32MP157CACx.tap halted
1 STM32MP157CACx.ap2 mem_ap little STM32MP157CACx.tap halted
2 STM32MP157CACx.axi mem_ap little STM32MP157CACx.tap halted
3 STM32MP157CACx.cpu0 cortex_a little STM32MP157CACx.tap halted
4 STM32MP157CACx.cpu1 cortex_a little STM32MP157CACx.tap running
5* STM32MP157CACx.cm4 cortex_m little STM32MP157CACx.tap reset
Before the command was issued, all targets but the cm4 were in the running state (the cm4 is always stuck in the reset state).
How can I access the core and load a program into it ?
Tool versions and configuration:
- STM32CubeIDE 1.4.0 on Ubuntu 20.04 (I use the provided OpenOCD)
- STlink V2 with the latest firmware
- Debug connection: SWD at 1.8 MHz (higher clock rates result in communication failure due to electrical contraints, lower clock rates do not change the result)
- Debug mode setup: Connect under reset, Enable debug in low power mode and Stop watchdog counter when halt are both enabled
