RGMII PHY connection doesn't come up 1000Mbps only 100Mbps

tzsolt · ‎2022-01-19

I use a STM32MP157C and connected to MAX24287 PHY by RGMII.

After linux booted there is only 100Mbps connection - I put the PHY into Diagnostic Loopback Mode and the situation is the same.

My dts:

&ethernet0{

pinctrl-names = "default", "sleep";

pinctrl-0 = <&eth1_pins_mx>;

pinctrl-1 = <&eth1_sleep_pins_mx>;

status = "okay";

/* USER CODE BEGIN ethernet0 */

phy-mode = "rgmii-id";

max-speed = <1000>;

phy-handle = <&phy0>;

mdio0 {

#address-cells = <1>;

#size-cells = <0>;

compatible = "snps,dwmac-mdio";

reset-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;

reset-delay-us = <10000>;

post-reset-delay-us = <1000>;

phy0: ethernet-phy@3 {

reg = <3>;

sfp;

/* compatible = "ethernet-phy-ieee802.3-c22"; */

/* interrupt-parent = <&gpioa>; */

/* interrupts = <9 IRQ_TYPE_EDGE_FALLING>; */

};

/* USER CODE END ethernet0 */

};

The PHY has 25MHz external clock, it gives 125MHz RX_CLK clock to the MAC, and the MAC would have give 125MHz TX_CLK (as GTX_CLK) to the PHY.

But with auto-negotiation the output on TX_CLK is only 25Mhz as 100Mbps.

This readable in the MAC registers:

devmem 0x50000A10 w 0x10800

devmem 0x50020004

0x00200000

devmem 0x500008FC

0x00000000

devmem 0x50000218

0x01004701

devmem 0x5800a000

0x0807E203

here ought to be 0x08072203 but the mac_speed_o[1] bit is "0" after negotiation.

Operating mode configuration register (ETH_MACCR)

Address offset: 0x0000

Reset value: 0x0000 8000

Bit 15 PS: Port Select

This bit selects the Ethernet line speed.

0: For 1000 Mbps operations

1: For 10 or 100 Mbps operations

In 10 or 100 Mbps operations, this bit, along with Bit 14, selects the exact line speed. In the

10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is readonly (RO) with appropriate value. In default 10/100/1000 Mbps configurations, this bit is readwrite (rw). The mac_speed_o[1] signal reflects the value of this bit.

Debug result from MAC registers:

What could be the bad settings?

I could not have any idea more.

Thank you.

Kevin HUBER · ‎2022-01-24

Hello @Tóth Zsolt ,

Did you plugged an ethernet cable on the port ethernet?

Because I made a test on my STM32MP157C-DK2 board by doing a new project from scratch on CubeMx, with ETH1 enabled with a clock from Crystal on PHY, CLK125 from PHY.

With a config ethernet0 in the DTS similar to your DTS:

&ethernet0{
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&eth1_pins_mx>;
	pinctrl-1 = <&eth1_sleep_pins_mx>;
	status = "okay";
 
	/* USER CODE BEGIN ethernet0 */
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	phy-handle = <&phy0>;
	nvmem-cells = <&ethernet_mac_address>;
	nvmem-cell-names = "mac-address";
 
	mdio0{
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
 
		phy0:ethernet-phy@0{
			reg = <0>;
		};
	};
	/* USER CODE END ethernet0 */
};

On linux, I got the same result that you by dumping 0x5800a000 with the bit 15 PS set to 1:

root@stm32mp1:~# devmem2 0x5800a000 
 
/dev/mem opened.
 
Memory mapped at address 0xb6f45000.
 
Value at address 0x5800A000 (0xb6f45000): 0x8078203

But once I plug the ethernet cable (at least Cat 5+), the configuration is automatically updated by Linux:

root@stm32mp1:~# [ 8662.875529] stm32-dwmac 5800a000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
 
[ 8662.882686] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
 
 
 
root@stm32mp1:~# devmem2 0x5800a000 
 
/dev/mem opened.
 
Memory mapped at address 0xb6f37000.
 
Value at address 0x5800A000 (0xb6f37000): 0x8072203

and the bit 15 PS switches to 0 as expected.

To help you, can I have more information about your configuration?

Which kind of clock are you using?

There is on the wiki some detailed example of the dts to use and what you have to take care, regarding your kind of clock: https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RGMII_with_Crystal_on_PHY-2C_CLK125_from_PHY_-28Reference_clock_-28standard_RGMII_clock_name-29_is_provided_by_a_Phy_Crystal-29

Which version of OpenStLinux are you using?
What "sfp;" means in your DTS?

Regards,

Kevin

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

tzsolt · ‎2022-01-24

Dear Kevin,

first of all thank you to care about my issue!

So, here are my answer:

in my hardware the STM32MP157C processor connected to the MAX24287 PHY which converts the signals to 1000BaseX form and it connects to a SFP module with fiber! This fiber goes to an media converter which holds the same SPF module and the converted signal connected to my PC by RJ45 TP cable.

To your first question - yes everything connected to each other.

Yes I read the wiki you mentioned several times and I use the

"3.3.4 RGMII with Crystal on PHY, CLK125 from PHY (Reference clock (standard RGMII clock name) is provided by a Phy Crystal)" description.

I have external 25MHz oscillator on the PHY, it gives 125MHz clock to the STM32 processor on pin ENET_CLK125 PG5 and ENET_RXC on pin PA1. The processor need to give 125MHz clock to the PHY on pin ENET_TXC PG4.

I use this version: "en.SOURCES-kernel-stm32mp1-openstlinux-5.10-dunfell-mp1-21-11-17.tar.xz"

I had no any idea so I tried this "sfp" because I use an SFP cage with an SFP Gigabit module.

One more thing I found, maybe there is problem with the PHY reset timing? I found this:

https://github.com/karo-electronics/meta-karo-stm/blob/4.19.49-thud/recipes-kernel/linux/linux-karo/phy-reset-bugfix.patch

Regards: Zsolt

tzsolt · ‎2022-01-24

Hello,

my another idea: something wrong happen, when the auto-negotiation occur.

If I know correctly the PHY tell to the MAC what speed could connect and the MAC use the same speed afterward. Somehow they could not agree on the 1000Mbps speed...

Here is our log with another kernel but the result is the same:

root@mf157:~# phytool write eth0/0x4/0x0 0x5000 <- no fiber cable in the SPF module, we put it into Diagnostic Loopback mode

root@mf157:~# [ 92.171745] stm32-dwmac 5800a000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx <- link come up

[ 92.179019] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

root@mf157:~# ethtool eth0

Settings for eth0:

Supported ports: [ TP MII ]

Supported link modes: 10baseT/Half 10baseT/Full

100baseT/Half 100baseT/Full

Supported pause frame use: Symmetric Receive-only

Supports auto-negotiation: Yes

Supported FEC modes: Not reported

Advertised link modes: 10baseT/Half 10baseT/Full

100baseT/Half 100baseT/Full

Advertised pause frame use: Symmetric Receive-only

Advertised auto-negotiation: Yes

Advertised FEC modes: Not reported

Link partner advertised link modes: 10baseT/Half 10baseT/Full

100baseT/Half 100baseT/Full

Link partner advertised pause frame use: Symmetric Receive-only

Link partner advertised auto-negotiation: Yes

Link partner advertised FEC modes: Not reported

Speed: 100Mb/s

Duplex: Full

Auto-negotiation: on

Port: MII

PHYAD: 4

Transceiver: external

Supports Wake-on: d

Wake-on: d

Current message level: 0x0000003f (63)

drv probe link timer ifdown ifup

Link detected: yes

As you can see neither of them advertise 1000Mbps!

OlivierK · ‎2022-01-26

Hello tzsolt (Community Member)

/* USER CODE BEGIN ethernet0 */

phy-mode = "rgmii-id";

Is the phy doing HW retiming on RX/TX pins? Do you have any pull-ups on these lines?

Otherwise to let the MAC control the retiming you should use:

phy-mode = "rgmii"

I guess you have verified your h/w bootstrap connections on the phy itself too?

Regards,

Olivier

OlivierK · ‎2022-01-26

You should have at least in the supported link modes:

root@stm32mp1:~# ethtool eth0

Settings for eth0:

Supported ports: [ TP MII ]

Supported link modes: 10baseT/Half 10baseT/Full

100baseT/Half 100baseT/Full

1000baseT/Full

tzsolt · ‎2022-01-26

Yes, it could do retiming, but not exactly standard:

"The MAX24287 data path latencies are shown in Table 6-21 below. These latencies exceed the full-duplex delay

constraints in 802.3 Table 36-9b. Therefore MAX24287 may not be compatible with PAUSE operation as specified

in 802.3 Clause 31."

so I changed the phy-mode to "rgmii-id" - the result is the same.

Yes, I have verified several times the bootstrap settings.

***********************************************************************

Maybe it could be problems with PHY:

"On the receive RGMII interface the MAX24287 does not report in-band status for link state, clock speed and duplex during normal inter-frame. This status indication is defined as optional in the RGMII specification."

or

"MAX24287 supports preamble suppression. This allows quicker bursts of read and write transfers to occur by shortening the minimum transfer cycle time from 65 clock periods to 33 clock periods. There must be at least a 32-bit preamble on the first transfer after reset, but on subsequent transfers the preamble can be suppressed or shortened. When the preamble is completely suppressed the 0 in the ST symbol follows the single IDLE Z, which is one clock period duration."

or

"The MAX24287 does not support the 802.3 clause 45 MDIO extensions. "

or

"The MAX24287's MDIO interface is compliant to IEEE 802.3 clause 22. MAX24287 always behaves as a PHY on the MDIO bus. Because MAX24287 is not a complete PHY but rather a device that sits between a MAC and a PHY, it implements only a subset of the registers and register fields specified in 802.3 clause 22 as shown in the table below."

I don't see 1000baseT/Full as Supported link modes...

tzsolt · ‎2022-01-26

Yes, it is very strange and I don't understand why I could not see in the supported modes: 1000baseT/Full ???

OlivierK · ‎2022-01-26

What happen if you do:

ethtool -s eth0 speed 1000 duplex full autoneg off

tzsolt · ‎2022-01-26

root@qsmp-1570:/home# ./ethtool -s eth0 speed 1000 duplex full autoneg off

[ 668.730661] stm32-dwmac 5800a000.ethernet eth0: Link is Down

root@qsmp-1570:/home# [ 669.352174] stm32-dwmac 5800a000.ethernet eth0: Link is Up - 10Mbps/Half - flow control off

root@qsmp-1570:/home# ./ethtool eth0

Settings for eth0:

Supported ports: [ TP MII ]

Supported link modes: 10baseT/Half 10baseT/Full

100baseT/Half 100baseT/Full

Supported pause frame use: Symmetric Receive-only

Supports auto-negotiation: Yes

Supported FEC modes: Not reported

Advertised link modes: 10baseT/Half 10baseT/Full

100baseT/Half 100baseT/Full

Advertised pause frame use: Symmetric Receive-only

Advertised auto-negotiation: No

Advertised FEC modes: Not reported

Speed: 10Mb/s

Duplex: Half

Auto-negotiation: off

Port: MII

PHYAD: 4

Transceiver: external

Supports Wake-on: ug

Wake-on: d

Current message level: 0x0000003f (63)

drv probe link timer ifdown ifup

Link detected: yes

root@qsmp-1570:/home#