Hi @GatienC
Looks like there are other issues in my case.
One thing I’ve identified is that the stpmic driver and the surrounding codebase have changed significantly. This can possibly why the code is crashing at the below point:
DFU alt info setting: done
D/TC:0 sm_platform_handler:95 VBDBG:sm_platform_handler:95: OPTEE_SMC_OWNER_SIP
D/TC:0 sip_service:36 VBDBG:sip_service:36: calling pwr_scv_handler
D/TC:0 pwr_scv_handler:56 PWR service: write 0x40000100 at offset 0xc
F/TC:0 pwr_scv_handler:72 wrt off c=40000100 => 40000100
D/TC:0 sip_service:39 VBDBG:sip_service:39: Backtrace:
E/TC:0 TEE load address @ 0xde000000
E/TC:0 Call stack:
E/TC:0 0xde003511
E/TC:0 0xde0315ef
E/TC:0 0xde031731
E/TC:0 0xde007205
E/TC:0 0xde007098
D/TC:0 sm_platform_handler:95 VBDBG:sm_platform_handler:95: OPTEE_SMC_OWNER_SIP
D/TC:0 sip_service:36 VBDBG:sip_service:36: calling pwr_scv_handler
D/TC:0 pwr_scv_handler:56 PWR service: write 0xd0000100 at offset 0xc
F/TC:0 pwr_scv_handler:72 wrt off c=50000100 => d0000100
D/TC:0 sip_service:39 VBDBG:sip_service:39: Backtrace:
E/TC:0 TEE load address @ 0xde000000
E/TC:0 Call stack:
E/TC:0 0xde003511
E/TC:0 0xde0315ef
E/TC:0 0xde031731
E/TC:0 0xde007205
E/TC:0 0xde007098
Looks like it is trying to power up the system but crashing. Apologies for the speculation but the traces from pwr_scv_handler give me a hint towards that.
We previously used a custom optee patch for our board (below), but now when I try to cherry-pick the changes, it appears the structure has changed quite a bit.
Adds option to device tree for changing current limit on pwr_sw2 output for a stpmic1 from 600mA to 1100mA. option in device tree is:
st,regulator-ocp-1a;
And needs setting in the relevant node.
---
.../arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c | 3 +++
core/drivers/regulator/core.c | 4 ++++
core/drivers/stpmic1.c | 14 ++++++++++++++
core/include/drivers/regulator.h | 2 ++
core/include/drivers/stpmic1.h | 8 ++++++++
5 files changed, 31 insertions(+)
diff --git a/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c b/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c
index 4eda619..34b3839 100644
--- a/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c
+++ b/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pmic.c
@@ -311,6 +311,9 @@ static TEE_Result pmic_set_flag(const struct regul_desc *desc, uint16_t flag)
case REGUL_ENABLE_BYPASS:
ret = stpmic1_regulator_bypass_mode_set(desc->node_name);
break;
+ case REGUL_ENABLE_OCP1A:
+ ret = stpmic1_regulator_ocp_1a_set(desc->node_name);
+ break;
default:
DMSG("Invalid flag %#"PRIx16, flag);
panic();
diff --git a/core/drivers/regulator/core.c b/core/drivers/regulator/core.c
index d4dc375..7b462fc 100644
--- a/core/drivers/regulator/core.c
+++ b/core/drivers/regulator/core.c
@@ -542,6 +542,10 @@ static struct regul_property flag_prop[] = {
.name = "st,regulator-bypass",
.flag = REGUL_ENABLE_BYPASS,
},
+ {
+ .name = "st,regulator-ocp-1a",
+ .flag = REGUL_ENABLE_OCP1A,
+ },
};
static TEE_Result parse_properties(const void *fdt, struct rdev *rdev, int node)
diff --git a/core/drivers/stpmic1.c b/core/drivers/stpmic1.c
index b558d6b..3449d92 100644
--- a/core/drivers/stpmic1.c
+++ b/core/drivers/stpmic1.c
@@ -27,6 +27,7 @@ struct regul_struct {
uint8_t mask_reset_pos;
uint8_t icc_reg;
uint8_t icc_mask;
+ uint8_t ocp1a_pos;
};
static struct i2c_handle_s *pmic_i2c_handle;
@@ -608,6 +609,7 @@ static const struct regul_struct regulators_table[] = {
.enable_pos = SWIN_SWOUT_ENABLED_POS,
.icc_reg = BUCK_ICC_TURNOFF_REG,
.icc_mask = PWR_SW2_ICC_SHIFT,
+ .ocp1a_pos = OCP_LIMIT_HIGH_POS,
},
};
@@ -787,6 +789,18 @@ int stpmic1_regulator_bypass_mode_set(const char *name)
LDO3_BYPASS | LDO_VOLTAGE_MASK);
}
+int stpmic1_regulator_ocp_1a_set(const char *name)
+{
+ const struct regul_struct *regul = get_regulator_data(name);
+
+ if (!regul->ocp1a_pos )
+ return -1;
+
+ return stpmic1_register_update(regul->control_reg,
+ BIT(regul->ocp1a_pos),
+ BIT(regul->ocp1a_pos));
+}
+
int stpmic1_active_discharge_mode_set(const char *name)
{
if (!strncmp(name, "pwr_sw1", 7))
diff --git a/core/include/drivers/regulator.h b/core/include/drivers/regulator.h
index 827b681..a999d87 100644
--- a/core/include/drivers/regulator.h
+++ b/core/include/drivers/regulator.h
@@ -46,6 +46,8 @@ int plat_get_lp_mode_count(void);
#define REGUL_SINK_SOURCE BIT(6)
/* st,regulator-bypass: set the regulator in bypass mode */
#define REGUL_ENABLE_BYPASS BIT(7)
+/* st,regulator-bypass: set the regulator in 1A over current protection mode */
+#define REGUL_ENABLE_OCP1A BIT(8)
struct rdev *regulator_get_by_node_name(const char *node_name);
struct rdev *regulator_get_by_regulator_name(const char *reg_name);
diff --git a/core/include/drivers/stpmic1.h b/core/include/drivers/stpmic1.h
index 5fe4823..502dadc 100644
--- a/core/include/drivers/stpmic1.h
+++ b/core/include/drivers/stpmic1.h
@@ -259,6 +259,14 @@ int stpmic1_lp_reg_on_off(const char *name, uint8_t enable);
int stpmic1_lp_set_mode(const char *name, uint8_t hplp);
int stpmic1_lp_set_voltage(const char *name, uint16_t millivolts);
+/**
+ * @brief INDRA specific creation to set 1A limit on pwr_sw2 as there was no mapping of register option to device tree settings
+ *
+ * @param name name of regulator to set option for (only works for pwr_sw2)
+ * @return int some kind of error value TODO: improve this when function is written
+*/
+int stpmic1_regulator_ocp_1a_set(const char *name);
+
#ifdef CFG_STM32MP15
/*
* Specific API for controlling regulators driven from STPMIC1 device
--
2.25.1
Would you mind taking a look at the attached patch and advising on how best to adapt these changes to the new stpmic driver in the optee-os repository?
I really appreciate your help.
Best regards,
Vivek
