Request for IBIS model for STM32MP157CAC3 DDR + high-speed IO (DDR, SDMMC, Ethernet)

[AvikalpF]

Dear ST Community,
I am currently working on a custom hardware design based on the STM32MP157CAC3 MPU, which includes LPDDR3 memory (Micron MT52L256M32D1PF) and multiple high-speed interfaces.
As part of my signal integrity and high-speed design validation process, I need simulation models to conduct accurate analysis.
I want to request the following:

IBIS models for STM32MP157CAC3, specifically covering:

1. DDR interface (LPDDR2/LPDDR3 controller)

2. SDMMC interface

3. Any other relevant high-speed I/Os(MIPI, LTDC, DCMI, SDMMC)

S-parameter models (if available) for:

1. High-speed I/O buffers

2. DDR interface pins or PHY

Any additional resources that may support SI/PI analysis, such as:

1. IBIS-AMI models (if available)

2. Reference simulation setups

3. Application notes related to DDR signal integrity

Project details:

Custom PCB (not a direct copy of STM32MP1 DK2)

LPDDR3 operating btw 300 - 800 MHz

Goal: Pre-layout and post-layout SI validation (HyperLynx/ADS

I understand that some of these models may require NDA access. I am willing to follow the necessary process if required.

Please let me know the appropriate steps to obtain these files.

[PatrickF]

Hi,

What you are asking for is already available in the product page (https://www.st.com/en/microcontrollers-microprocessors/stm32mp157c.html), e.g.

• STM32MP15x IBIS file
• AN4803 High-speed SI simulations using IBIS and board-level simulations using HyperLynx® SI on STM32 MCUs and MPUs
  
• AN5168 How to configure DDR on STM32MP1 MPUs
• AN5122 STM32MP1 Series DDR memory routing guidelines
  
• STM32MP15x Series DDR memory routing guidelines examples

Regards.