I'm using the mp215 with ddr3l (x16) and an ISSI dram ic that is 8Gb (1 gigabyte) which means it's a dual rank configuration compared to a more typical half gigabyte. As far as im aware all 1GB ddr3 dram ic's are dual rank.
In AN5723 6.1 Note it says "8 Gbit DDR3 defined by JEDEC is uncommon. Practically, DDR3L density is limited to 4 Gbits (max = 1 Gbyte in total). Single rank only is required. ".
As far as I understand it it says it's not possible. However this is an older AN and i think it's for the mp25 series only (im using the mp21).
However in the ST Wiki "How to setup the DDR configuration" section 5 the exact opposite is implied. This whole section repeatedly describes a "concrete example" of swapping the swapping the mp215-dk's lpddr4 out with a 1GB ddr3 ic. Also using a theoretical dtsi called "stm32mp21-ddr3-1x8Gbits-1x16bits-800MHz.dtsi" and define "DDR_MEM_SIZE 0x40000000" which is 1GB. So this is conflicting info because i dont see how 1gb ddr3 is possible if it isn't dual rank.
https://wiki.st.com/stm32mpu/wiki/How_to_setup_the_DDR_configuration#STM32MP2_series
However another conflict is in cubemx. I have 16 bit ddr3 set for the DDR_CTRL_PHY config. And i even have Density set to 8Gb implying dual rank. but the greyed out "user input basic" option has NUMRANK_DFI0 set to 1 and it can't be changed. so i don't know how im even supposed to generate a valid dtsi for my case.
Another conflict on top of that is the mp21 control signals DDR_A2 and DDR_A6 pins are CS_N0 and CS_N1. Those are chip select pins ranks. Once again implying it is possible. So which is it? is it supported or not and if it is how do i set it as dual rank in cubemx.
To reiterate on what st resources say about dual rank ddr3.
- AN5723 says it's not possible
- Wiki says it is.
-Cubemx implies it's not.
-Routing pins available implies it is.
