How Integrate and Handle the First-Time Boot Process for STPMIC1x with an STM32MP15x MPU

[TD_P1]

Hello,

I am integrating an STPMIC1x component to power my STM32MP153C-based system. This design is closely following the STM32MP157F-DK2 schematic found here. The issue comes from the fact that some of the default output voltages for STPMIC1APQR used in the design do not align with the necessary power inputs for some of the peripherals, namely the DDR3L chip. For example (in the EVK schematic), VDD_DDR on BUCK2 is by default Rank0 and set to 1.1V, which does not meet the DDR3L specification of 1.35V.

The STPMIC1x datasheet implies that the A/B/D/E part numbers can provide the correct voltages for VDD and VDD_CORE by default (through Rank1, Rank2, or Rank3 outputs), and then the STPMIC1A/B/D/E can be (re)programmed by the MPU to provide the correct voltages on its other outputs such as its DDR3L peripheral.

Q: Is this (re)programming of the STPMIC1x chips handled early in the boot process through OpenSTLinux and carried out on I2C4 from the MPU? If so, where does this occur in the codebase? Otherwise, do these STPMIC1x chips require pre-programming from an external programmer prior to use in a board design?

Table of default configurations:

[MBG]

Is there any update on this? I am doing something similar and would also like to know the answer.

[PatrickF]

Hi @TD_P1 

the STPMIC voltage at rank 0 are not started automatically (e.g. the VDD_DDR BUCK2). You don't care of default voltage for those rank 0.

FSBL SW (e.g. TF-A) will use I2C to start relevant regulators at the voltage as defined in the Device Tree (if needed, in correct sequence as per DDR requirements, before DDR initialization take place).

e.g. https://wiki.st.com/stm32mpu/wiki/Regulator_overview#PMIC 

Regards.