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Synchronizing Time Between A7 and M4 Cores on STM32: Accessing STGEN Timer from A7

Associate II


I need to synchronize the time between the A7 and M4 cores. While I found some resources on the ST Community that accessing the STGEN timer from the A7 side.

the article is below

So, I tried this on A7 too.

for reading/writing peripheral registers from the A7 core is outlined in STWiki article.

I think accessing /dev/mem offer a same capability. I tried and successfully employed this approach for UART4. However, I failed when it comes to reading the STGENR using this method.

Could someone provide guidance on how I might access the STGEN timer from the A7 core? If there's a more efficient or recommended way to synchronize the time between the A7 and M4 cores, that information would be invaluable as well.

Thank you for your assistance.

ST Employee

Hello @MJo.3

You can check these links : 

Hope that helps!

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Associate II

Hello, @Sarra.S 

I read the two links. but still, I can't understand how to access the STGENR.

the first link says CNTFRQ register but it isn't listed on manual.

in second one, I guess this part "4 Software frameworks and drivers " would be an answer but it just send me code without any explanations.

So i checked the code and find

mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));

static inline void mmio_write_32(uintptr_t addr, uint32_t value)
*(volatile uint32_t*)addr = value;


I think it's the same approach.

So, I guess permission is the key. 

how to change the permission to read this value in user space?

Associate II

I said it's about permission but STGENR can be accessed in non-secure mode.

Does non-secure mode mean A7 Linux userspace?