2019-09-04 06:21 AM
2019-09-04 11:37 PM
Even if HW could permit that, in STM32MP1 series, we do not offer any support for USBPHYC, USBH or OTG IPs configuration on Cortex-M4 side.
Please also note that OTG device in High-Speed mode is required to be managed by Cortex-A7 during Flash programming phases (but Cortex-M4 is not used during this sequence).
Please note that both USB share some ressources (e.g. same PLL inside USBPHYC) which make sharing USBH under Linux Control and OTG under M4 control very complex when we talk about init and low power modes.
We do not recommend using USB from Cortex-M4 which should be managed mostly as a coprocessor.
Could you share the use case you have in mind ?
2019-09-04 11:37 PM
Even if HW could permit that, in STM32MP1 series, we do not offer any support for USBPHYC, USBH or OTG IPs configuration on Cortex-M4 side.
Please also note that OTG device in High-Speed mode is required to be managed by Cortex-A7 during Flash programming phases (but Cortex-M4 is not used during this sequence).
Please note that both USB share some ressources (e.g. same PLL inside USBPHYC) which make sharing USBH under Linux Control and OTG under M4 control very complex when we talk about init and low power modes.
We do not recommend using USB from Cortex-M4 which should be managed mostly as a coprocessor.
Could you share the use case you have in mind ?
2019-09-05 10:51 AM
Thanks for your answer.
Use case:
We have now USB host - USB device connection and host have few (non-standard) commands that device can't handle. So we need an "intermediator"-device, which catches non-standard commands from USB traffic and gives suitable reply to them. Standard commands shall be transmitted to the USB-device which gives a reply to them. USB-traffic is high speed (HS).