I am using UART5 on an STM32MP151 to communicate with an external processor. The Cortex-A7 is running Linux and DMA is in use for both receive and transmit. Hardware flow control is also enabled and the transfer rate is 6 Mbps. Currently we are running test code to repeatedly send messages between the processors in both directions simultaneously. During this test, eventually the MP151 will send part of a message, and then the transmission will stop and never complete. I have verified this both by examining what is received on the other processor, as well as by using an oscilloscope. Here is the data that I have about the problem:
- Hardware flow control is not activating in this scenario, as verified by the oscilloscope
- The DMA transfer is still active. This has been verified by noting that the EN bit of the SCR register is still set and the SNDTR register still has the correct count of the remaining bytes that haven't yet been sent.
- The serial port is still active. This has been verified by noting that the DMAT bit of CR3 is still set , the ISR register shows the TXFIFO is empty, the TC bit of the ISR register is set, and the ISR register has no errors indicated.
By examining the DMA and UART registers, it appears that for some reason the DMA has stopped loading bytes into the UART. Nothing looks out of the ordinary except one thing: the FEIF bit of HISR indicates that a FIFO error event occurred. This is strange because the DMA is operating in direct mode. I came across this statement in the reference manual:
In direct mode, the FIFO error flag can also be set under the following conditions:
• In the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory bus is not granted for several peripheral requests.
• In the memory-to-peripheral mode, an underrun condition may occur if the memory bus has not been granted before a peripheral request occurs.
I'm wondering if this FIFO error flag could be why the transmit DMA transfer stopped. My questions are:
- Does it seem reasonable that this would be why the DMA transfer stopped?
- What exactly does "if the memory bus has not been granted before a peripheral request occurs" mean?
- What can I do to address this problem?
Thank you for your help,
Brian
EDIT: It seems there are FIFO errors asserted in direct mode when the transfer is successful too, so I'm guessing that maybe the FIFO error doesn't have anything to do with it. To clarify, the DMA transfer is in progress when it just stops in the middle of the transfer for no apparent reason. I have done a test where after the transfer stops I clear the UART DMAT bit and then set the UART DMAT bit. If I do that then the DMA transfer resumes. This suggests to me that the DMA is stuck. What could possibly cause this?
