2025-10-21 3:07 PM
Hi all, apologies if I have missed the answer to this question in previous posts.
I understand that according to the datasheet, the maximum input voltage of FT_xx (and even TT) pins is 3.9V even when VDD, VDDA, VDDRF, and VDDSMPS = 0V. From my understanding, this is possible because of the logic level shifters that have been implemented in the design of the chip. These logic level shifters are powered by the VCORE domain according to the datasheet.
Based on the datasheet, if the microcontroller chip is put into SHUTDOWN mode, the VCORE domain is powered off. Does this mean that the maximum input voltage on the FT_xx pins become 0V? Thank you for clarifying this!
2025-10-21 3:46 PM
For FT_xx pins, the max input voltage is 3.6 V when the chip is not powered (VDD = VDDA = 0 V). For TT pins, it is 0.3 V.