The QSPI_DdrHoldHalfCycle parameter is not declared in the QSPI HAL file of the STM32WBxx as the DHHC bit presenting the delay of the data output using analog delay in DDR mode, is disabled in the QUADSPI communication configuration register, referring to the 15.5.6 section of the RM0434. It is not integrated in this product.
DHHC and FRCM bits (30 and 29) seem to be non-existent in QUADSPI_CCR for this MCU. Maybe they simply don't work as desired or ST considerd them as not useful or whatever ...
But you could try to set them anyway, maybe they do work contrary to RM?
The QSPI_DdrHoldHalfCycle parameter is not declared in the QSPI HAL file of the STM32WBxx as the DHHC bit presenting the delay of the data output using analog delay in DDR mode, is disabled in the QUADSPI communication configuration register, referring to the 15.5.6 section of the RM0434. It is not integrated in this product.
