STM32L4+ What are the best external memory options for a frame buffer for the LTDC?

[Geoffrey Furman]

STM32L4+

Support for 640x400 60Hz LCD with 24-bit video.

Display bandwidth requirement is approximately 60 MBytes/sec average, 81MBps max.

I was planning on HyperRAM because I wrote and FPGA interface to one and understand it.

The STM32L4S and L4R datasheet specs a much slower clock frequency for HyperRAM than HyperFlash with HyperRAM having a prescaler not included for the other. Does anyone understand why this is?

Is there a better bandwidth option? xSPI, PSRAM?

I am hoping for 1.8V operation, small device packages.

[Alex - APMemory]

Hi, 

- From a BW point of view, OPI PSRAM should be good enough for your use case with optimized pin count (QSPI PSRAM not enough, HPI PSRAM possible upon MCU support). IoT RAM is supporting 1.8V, as well as WLCSP ultra small package.

- STM32L4S and L4R are not supporting Octal RAM properly (whichever HyperRAM, Xccela, OctaRAM protocols). (See details  https://www.st.com/content/ccc/resource/technical/document/errata_sheet/group0/ef/74/70/f6/89/a9/42/3f/DM00371862/files/DM00371862.pdf/jcr:content/translations/en.DM00371862.pdf)

If you can switch to STM32L4P or other SoC L5/U5/H5/, Octal RAM is the best memory option (pincount, power, simplicity...) with a wide range of density from 64Mb (APS6408L...) to 512Mb (APS512XXN...), up to 1GB/s, in BGA24 or WLCSP.

- for info, some user which had no other choice than using STM32L4R/S and OPI (couldn't handle FMC/SDRAM/ADMUX high pin count), were able to run IoT RAM (APS6408L-OBM-BA) with STM32L4R9. Critical point is to avoid odd address write issue. In such case, you need to control your SW and access to the memory (at your own risk), either with direct simple access, or also for frame buffering adjusting parameter to the odd address write limitation (for example with a 2 bytes pixel, the DMA2D should be 2 bytes aligned, so no odd address access). As mentioned in errata, this is not supported by ST.

Alex