STM32F417IGT6 FSMC A25 HardFault

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Posted on April 12, 2015 at 11:16

I have an ILI9325 TFT LCD connected to an F417IGT6 via FSMC Bank 1, Region 1, using 16-bits.

The ILI9325 has an 8080-style interface, and FSMC A25 has been selected to drive register select as per AN2790 Figure 3 for 176-pin devices.I calculated A25 offset to be 0x2000000 from Bank 1 Region 1 start address (which according to RM0090 is at 0x60000000), giving 0x62000000.At this address I am not seeing anything on the logic analyser. A25 is PG14 on the 417IGT6 and if set to output push pull, can be driven successfully, proven by inspection with the logic analyser again, ruling out a hardware issue.When I configure the FSMC with A16 or A19, all is fine as well and the LCD works perfectly, proving the the remainder of the FSMC setup is correct.Clive and Andy Brown's posts elsewhere on this forum, along with a broader search on Google and inspection of the working addresses for A16 and A19, lead me to suspect that the A25 address might actually be 0x64000000, but when writing to this address the MCU hardfaults.Looking at RM0090, 0x64000000 looks to be the start of region 2 of Bank 1.My questions is whether my calculated offset of 0x2000000 is even correct at all and if not, a bit of insight on the hardfault from a more experienced developer.Below are some of the SCB register contents at exception:

HFSR: 0x40000000

CFSR: 0x400

MMFAR: 0xE000ED34

BFAR: 0xE000ED38

DFSR: 0xA

Thanks #lcd #fsmc #stm32f417

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Posted on April 12, 2015 at 14:15

But in 16-bit mode don't all the address bits shift?

PG13 FSMC_A23 would be +0x02000000 (ie 0x62000000) In 8-bit mode PG14 FSMC_A24 would be +0x02000000

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Posted on April 12, 2015 at 15:14

Thanks for your reply Clive.

That's my understanding of it as well, but I lose the plot when it comes to the addressing of A25 in 16-bit mode, since the shift would put the address of A25 at 0x68000000, which is beyond the start of the next region of Bank 1. Region 1 (Chip Select NE1) starts at 0x60000000, Region 2 (Chip Select NE2) starts at 0x64000000 etc...Does this mean A25 cannot be addressed? It seems that regardless of which region of bank 1 is chosen, the offset required for A25 in 16-bit mode always puts its address within the address space of the next region.Or am I missing something else?

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Posted on April 12, 2015 at 15:48

You have 4x 64MB (BYTE) windows via the external chip selects in the 256MB 0x60000000..0x6FFFFFFF space.

You're not going to have A25..A0 in the 16-bit space, you're going to have A24..A0 describing 16-bit words, 32Mx16-bit. This is the equivalent to A25..A1 in the 8-bit sense, shifted externally to reduce the pin count requirements. The ILI9325 has ONE address bit (register select), and it doesn't need to be a high order address bit. You get a Hard Fault at 0x64000000 because you don't have an active memory decoding in that bank.

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Posted on April 12, 2015 at 16:22Thanks Clive - that clears it up for me.