display glitch with STM32H757

[fb]

I'm using a 1280x800 pixel display with 72 MHz pixel clock, and an external SDRAM. Sometimes I see glitches like this, where parts of the image is horizontally displaced:

https://www.youtube.com/watch?v=_pluyvL0PvI

The SDRAM is the IS42S32200L with 32 bit data bus. The glitch only happens, when the CPU does other things, like updating a FPS counter on the display. When I stop the program with an infinite while loop, the display is fine.

The glitch happens much more often with a lower SDRAM speed. The video is with 100 MHz clock for the SDRAM. The LTDC is configured in 16 bit mode. So this should be nearly 3 times as much bandwidth as needed. But it also happens sometimes when I configure the SDRAM clock with the maximum allowed 200 MHz, but not as much.

I tried to change the AXI interconnect configuration, prioritizing the QoS setting for the LTDC controller, but no changes.

What can be the reason for the glitches and how to fix it?

[MM..1]

LTDC prebuffers data read appnote about this. 72MHz is little edge try use math

Test lower to 70 68 66 ... Optimize as described in appnote

[fb]

Thanks, do you have a link to the app note?

I don't think it is on the edge, because 100 MHz with 32 bit data interface means a little bit less than 3.2 Gbit/s, if burst mode is used. And 16 bit with 72 MHz needs only 1.1 Gbit/s. And it wouldn't explain why it also happens sometimes with 200 MHz clock, and why it doesn't happen when the CPU is running in an infinite loop. My assumption is that the AXI bus is blocked too long sometimes, which the AXI interconnect matrix QoS configuration should solve, but it didn't.

[MM..1]

LCD-TFT display controller (LTDC) on STM32 MCUs - Application note

[fb]

According to the application note, the highest pixel clock with STM32H757 and SDRAM with 32 bit is 150 MHz, for 16 bit mode. So the 72 MHz I'm using is not on the edge, as expected.

The line length is also a multiple of 128, so it can do all reads with burst reads, says the application note.

But there are some other tips about speculative read access, SDRAM RBURST mode, and cache settings. Will try this next, maybe it solves the problem.

[MM..1]

Are you sure your display isnt 800x1280

[fb]

Yes, I'm sure it is 1280x800. Sorry for the bad mobile phone recording.

[MM..1]

150 is teoretical max. Your bus need space to other work. And if D2DMA is used ...

for 24 bit is max only 64. Try locate code and show here, what produce glitch. For example update text or ... Too some LTDC interrupt driver implementation is buggy usw.