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Linas L
Linas L
Senior
December 11, 2022
Question

Crossing SRAM1/2/3 with DMA

  • December 11, 2022
  • 4 replies
  • 2227 views

Hello,

In my project I need a lot of memory, like 652kB. For that I will use STM32U5 MCU.

Compiler does allow to make array I need, because total amount of SRAM is 786 KB.

But it crosses multiple internal SRAM banks. It looks like addresses are in line so where are no gaps.

0693W00000WKiY5QAL.png 

Is it legal to do that ? it would be nice if I don't need to play around with DMA to setup multiple instances to jump between regions.

This topic has been closed for replies.

4 replies

waclawek.jan
waclawek.jan
Super User
December 11, 2022

I don't use the 'U5 but I see no obvious problem using several SRAMs for DMA, if they represent continuous address space. It defeats the primary purpose of having split SRAM areas, i.e. avoiding collisions in using a SRAM area by several busmasters, but whether this is a problem depends on the minute particularities of your application. You may want to devise a benchmark/test on a Nucleo or similar devboard to judge.

JW

Linas L
Linas LAuthor
Senior
December 11, 2022

It's for camera, so bus master will be only DMA, and only after TC it will be handled by CPU.

KDJEM.1
KDJEM.1
ST Technical Moderator
December 27, 2022

Hello @Linas L;

I recommend the “Application note Digital camera interface (DCMI) for STM32 MCUs�? (AN5020) and precisely STM32U5 system architecture Section. This application note mentioned DCMI application examples with different capture modes.

I hope this helps!

Kaouthar​ 

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waclawek.jan
waclawek.jan
Super User
December 11, 2022

Unless the processor is put to sleep during DMA-based acquisition, it accesses its static data/stack/heap in one of the SRAMs.

Looking at Figure 1. System architecture in RM0456, there's also an asymmetry in accessing the individual SRAM areas from the GPDMA in that SRAM1 is connected through what's called there a "fast bus multiplexer", the narrative explaining that those interconnections enable no-wait-state accesses while others impose at least one wait state. Again, this may be relevant only in the most constrained designs.

JW

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