2022-10-04 06:41 AM
I tried to make my project SBSFU compatible, by using 'STM32F769I_Discovery_2_Images_UserApp' example.
It is based on the STM32F756VGT6 microcontroller and I defined the load region on ITCM interface address range -0x200000 to 0x2FFFFF- instead of AXIM interface -0x8000000 to 0x80FFFFF-.
I did what is said in an5056 section 8.1 but unfortunately was not successful.
The compilation is O.K and when I look at the generated Hex files of SBSFU and the main project with ST-LINK UTILITY, the ranges are O.K and are as the ranges of the linker file.
But it seems when the postbuild wants to create the final binary file it misses the main project section and the SLOT_ACTIVE_1 is almost filled by 0xFF.
Here is my project's linker, mapping_fwimg.h, and mapping_sbsfu.h
#! armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -xc
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
#include "..\..\..\Linker_Common\MDK-ARM\mapping_sbsfu.h"
#include "..\..\..\Linker_Common\MDK-ARM\mapping_fwimg.h"
LR_ROM (SLOT_ACTIVE_1_START + 0x400) { ; Cortex-M7: align the init vectors on 0x400
vector_start (SLOT_ACTIVE_1_START + 0x400) FIXED VECTOR_SIZE {
*.o (RESET, +First)
}
ROM_region +0 {
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap starts at 1MB and grows upwards
ARM_LIB_HEAP 0x20000900 EMPTY 0x400 {
}
; Stack space starts at the end of the 2MB of RAM
; and grows downwards for 1KB (indicated by the negative length)
ARM_LIB_STACK 0x20000800 EMPTY -0x800 {
}
DTCMRAM_REGION 0x20000D00 0xCA0 {
.ANY (DTCMRAM)
}
RW_IRAM1 0x200019A0 0x0000E660 { ; RW data
.ANY (+RW +ZI)
}
SB_RAM_region (SE_REGION_RAM_END + 1) 0x0003D000 { ; RW data
.ANY (+RW +ZI)
}
ITCMRAM_REGION 0x00000000 0X3FFF {
.ANY (ITCMRAM)
}
}
; extra ROM region to make sure the binary size is a multiple of the AES block size (16 bytes) and F7 flash writing unit (4 bytes)
LR_ROM1(+0) ALIGN(16) {
ForAlignment +0 {
startup_stm32f756xx.o (ALIGNTOAESBLOCK,+Last)
}
}
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef MAPPING_FWIMG_H
#define MAPPING_FWIMG_H
/* Slots must be aligned on sector size */
/* swap Sector 5 : 256 kbytes */
#define SWAP_START 0x00240000
#define SWAP_END 0x0027FFFF
/* Active slot #1 : 1 sectors of 256 kbytes */
#define SLOT_ACTIVE_1_START 0x00280000
#define SLOT_ACTIVE_1_END 0x002BFFFF
#define SLOT_ACTIVE_1_HEADER SLOT_ACTIVE_1_START
/* Dwl slot #1 : 1 sectors of 256 kbytes */
#define SLOT_DWL_1_START 0x002C0000
#define SLOT_DWL_1_END 0x002FFFFF
/* Slots not configured */
#define SLOT_ACTIVE_2_HEADER 0x00000000
#define SLOT_ACTIVE_2_START 0x00000000
#define SLOT_ACTIVE_2_END 0x00000000
#define SLOT_ACTIVE_3_HEADER 0x00000000
#define SLOT_ACTIVE_3_START 0x00000000
#define SLOT_ACTIVE_3_END 0x00000000
#define SLOT_DWL_2_START 0x00000000
#define SLOT_DWL_2_END 0x00000000
#define SLOT_DWL_3_START 0x00000000
#define SLOT_DWL_3_END 0x00000000
#endif
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef MAPPING_SBSFU_H
#define MAPPING_SBSFU_H
/* SE Code region protected by protected area */
#define VECTOR_SIZE 0x400
#define ROM_START 0x0200000
#define SE_CODE_REGION_ROM_START (ROM_START + VECTOR_SIZE)
#define SE_CALLGATE_REGION_ROM_START (SE_CODE_REGION_ROM_START + 0x8)
#define SE_CALLGATE_REGION_ROM_END (SE_CODE_REGION_ROM_START + 0x1FF)
/* SE key region protected by protected area */
#define SE_KEY_REGION_ROM_START (SE_CALLGATE_REGION_ROM_END + 0x1)
#define SE_KEY_REGION_ROM_END (SE_KEY_REGION_ROM_START + 0xFF)
/* SE Startup: call before enabling protected area */
#define SE_STARTUP_REGION_ROM_START (SE_KEY_REGION_ROM_END + 0x1)
#define SE_CODE_NOKEY_REGION_ROM_START (SE_STARTUP_REGION_ROM_START + 0x100)
/* Aligned SE End at the end of the 1st 64Kbytes of flash, MPU protection isolation constraints */
#define SE_CODE_REGION_ROM_END 0x0020FFFF
/* SE IF ROM: used to locate Secure Engine interface code out of protected area */
#define SE_IF_REGION_ROM_START (SE_CODE_REGION_ROM_END + 0x1)
#define SE_IF_REGION_ROM_END (SE_IF_REGION_ROM_START + 0x8FF)
/* SBSFU Code region */
#define SB_REGION_ROM_START (SE_IF_REGION_ROM_END + 0x1)
/* Aligned SBSFU end at the end of the 1st 128Kbytes of FLASH, MPU protection isolation constraints */
#define SB_REGION_ROM_END 0x0021FFFF
/* ROM regions size definition */
#define SE_CALLGATE_REGION_ROM_SIZE (SE_CALLGATE_REGION_ROM_END - SE_CODE_REGION_ROM_START + 0x1)
#define SE_KEY_REGION_ROM_SIZE (SE_KEY_REGION_ROM_END - SE_KEY_REGION_ROM_START + 0x1)
#define SE_ROM_REGION_SIZE (SE_CODE_REGION_ROM_END - SE_CODE_NOKEY_REGION_ROM_START + 0x1)
#define SE_IF_ROM_REGION_SIZE (SE_IF_REGION_ROM_END - SE_IF_REGION_ROM_START + 0x1)
#define SB_ROM_REGION_SIZE (SB_REGION_ROM_END - SB_REGION_ROM_START + 0x1)
/* RAM section */
/* SE RAM1 region protected by protected area */
/* SE stack is placed 1st in RAM, stack overflow does not write on other RAM area */
#define SE_REGION_RAM_START 0x20010000
#define SE_REGION_RAM_STACK_TOP 0x20011000
#define SE_REGION_RAM_END 0x20012FFF
/* SBSFU RAM1 region */
#define SB_REGION_RAM_START (SE_REGION_RAM_END + 0x1)
#define SB_REGION_RAM_END 0x2004FFFF
#define SE_RAM_REGION_START (SE_REGION_RAM_STACK_TOP)
#define SE_RAM_REGION_SIZE (SE_REGION_RAM_END - SE_REGION_RAM_STACK_TOP + 0x1)
#define SB_RAM_REGION_SIZE (SB_REGION_RAM_END - SB_REGION_RAM_START + 0x1)
#endif
Is there anything that I'm doing wrong?
2022-10-06 12:50 AM
This is also my output.txt file:
block size =16
Magic: b'SFU1'!!
Magic: b'SFU1'!!
number of segment :2
0x2bc110
number of segment :3
0x2001c8
0x2096d0
Merging
SBSFU Base = 0x200000
Writing header = 0x2bbd10
APPLI Base = 0x2bc110
Writing to .\\..\\Binary\\\\SBSFU_PM2019.bin 770336
I think the problem is shown in these 2 lines:
Writing header = 0x2bbd10
APPLI Base = 0x2bc110
How the "Writing header = " is set?
2022-10-11 10:27 PM
Hmm, I think I found the problem.
There were some functions in my projects which were supposed to be executed from ITCM.
So they were declared like this:
void my_function(void) __attribute__((section ("ITCMRAM")));
block size =16
Magic: b'SFU1'!!
are missing from the end of the file. so is there any problem?
Here is my whole output.txt:
block size =16
Magic: b'SFU1'!!
Magic: b'SFU1'!!
number of segment :2
0x80badf8
number of segment :3
0x80001c8
0x80096c8
Merging
SBSFU Base = 0x8000000
Writing header = 0x8080000
APPLI Base = 0x8080400
Writing to .\\..\\Binary\\\\SBSFU_PM2019.bin 770576
2022-10-14 12:59 AM
Hello @ali rostami
Yes there is a bug in the prepareimage.py that does not take into account such ITCM case.
You should be able to fix this in the python script:
In function find_lowest_section
Replace
if lowest_addr == 0:
by
if sh_addr < 0x08000000:
pass
elif lowest_addr == 0:
This will exclude all addresses that are not flash.
To make this work you will also need to for usage of python in the postbuild script.
Best regards
Jocelyn
2022-10-14 10:32 PM
Thank you very much @Jocelyn RICARD
Sorry I couldn't understand. Do you mean this:
def find_lowest_section(elffile):
lowest_addr = 0
lowest_size = 0
for s in elffile.iter_sections():
if (s.header['sh_flags'] & elftools.elf.constants.SH_FLAGS.SHF_ALLOC) and (s.header.sh_type != '***_NOBITS'):
sh_addr = s.header['sh_addr'];
if sh_addr < 0x8000000:
lowest_addr = sh_addr
elif lowest_addr == 0:
lowest_addr = sh_addr
lowest_size = s.header['sh_size']
return lowest_addr, lowest_size
And would you please answer my third question too? Is my output.txt normal?