There are several peripherals that have a separate layer of protection based on privileged/unprivileged, here are some examples from the reference manual:
- MCE:
- 39.2 MCE main features
"AHB configuration port, privileged aware"
- RTC:
- 49.2 RTC main features
"Alarm A, alarm B, wake-up Timer and timestamp individual privilege protection"
A first question would be: What privilege is being talked about?
Is it the CPU's current (un)privileged mode when the CPU has sent the access request?
Or is it the CPU's current (un)privileged mode independent of whether the CPU has sent the access request?
Or is it any bus master's current (un)privileged mode (assuming every bus master has such concept) when that bus master has sent the access request?
It does appear that other bus masters have privilege-based protection:
- GPDMA:
- 12.2 GPDMA main features
"Privileged/unprivileged support:
- Support for privileged and unprivileged GPDMA transfers, independently at a
channel level
- Privileged-aware AHB slave port"
- HPDMA:
- 13.2 HPDMA main features
"Privileged/unprivileged support:
- Support for privileged and unprivileged HPDMA transfers, independently at a
channel level
- Privileged-aware AHB slave port"
but I suppose that that privilege-based protection is only applicable on accesses to their config registers and that that is not the same as an (un)privileged mode of the bus master itself.
A summarizing question by means of an example could be interesting here:
Is GPDMA able to access the RTC timer registers supposing that the RTC timer register privilege protection is activated, the GPDMA privilege protection is not activated, and that the CPU is running in unprivileged mode at the moment of launching the GPDMA request?
And to make it even more interesting, the same question with the addition of MPU protection only on the RTC timer registers to block unprivileged access?
