STM32N6 power supply simplification

[aroberts-figure]

I am working on an STM32N6 hardware design, and have reviewed both development kit reference designs (MB1939/MB1940). Both designs use the same power supply scheme, when using internal SMPS it has 2x 3V3 regulators and 3x 1V8 regulators.

I am interested in combining several power supplies if possible, notably:
1. Is it possible to tie all 3V3 together?
While AN5967 suggests to apply VDD33USB in the last step of power sequencing, the VDD33USB supply is noted to be independent of the other supplies within the N6, just like the VDDIOx supplies. The reference designs have tied VDDIO4 to VDD at 3.3V, which makes me believe I could also combine VDD33USB and VDD.
Aside from just VDD33USB and VDD, all the 3.3V peripherals on the dev kits come from the second 3V3 supply, can I tie all peripheral 3V3 to VDD33USB and VDD, so I have a single 3V3 rail on the PCB?
If not what about the STM32N6 disallows this?

2. Can I combine 1V8 for peripherals with VDD18AON?

Is there anything against connecting 1V8 for flash and ram and such with VDD18AON? since my VDDIO for those IO banks will be tied to VDD18AON anyways.


Overall, the power sequencing diagram only shows that VDD/VDDA18AON must be stable before VDDCORE, but it does not show any sort of required ramp time for the other supplies. Can I simply have a single 3V3 and 1V8 supply that ramp up, then VDDCORE comes up automatically afterwards?

[RomainR.]

Hello @aroberts-figure 

Please note that for the STM32N657-DK and NUCLEO-N657X-0Q boards, the VDDCore supplies are implemented in External SMPS mode. Therefore, the VDDCore 0.8V is generated by an external Buck regulator.

>“Beyond VDD33USB and VDD, all the 3.3V peripherals on the development kits come from the second 3V3 rail; can I tie all the 3.3V peripherals to VDD33USB and VDD, so I have a single 3V3 rail on the PCB?”

If your VDD = 3.3V, the mandatory sequence is to apply VDD + VDDA18AON, which will enable PWR_ON.
It is possible to group VDDA18AON with other 1.8V supplies (such as VDDA18PLL, VDDA18, VFFA18USB, etc.).
However, if you have a common 3.3V for all VDD, VDDIOx, and VDD33USB, they will be established before VDDA18USB. Therefore, it is recommended to sequence VDD33USB after VDDA18USB.
The reason is that on STM32N6, the VDDAxx 1.8V rails are mostly reserved for the system (internal oscillator, PLL, PHY, or OTP) and must appear and stable before the PHY supply (such as USB PHY).

> “Can I combine the 1V8 for peripherals with VDD18AON?”

 

Yes, this is possible, but under the condition that you respect the explanations above.

For powering an STM32N6, the design we recommend is as follows:

Always present:

• VDDA18AON
• VDD for VBAT + VDD + [VDDIO2 + VDDIO3] + VDDIO4 + VDDIO5 = 3.3V

Note 1: Here VDDIO2 + VDDIO3 = 3.3V for external memory at low-frequency data rate.

Enabled with PWR_ON:

• VDDA18 for VDDIO2 + VDDIO3 + VREFP + VDDA18ADC + VDDA18PLL + VDDA18USB
• VDD3V3 for VDD33USB
• VDD1V8 for VDDSMPS + VDDA18PMU (in case of internal SMPS usage on N6)

Note 2: Here VDDIO2 + VDDIO3 = 1.8V for external memory at high-frequency data rate.
Note 3: In external SMPS mode, VDDSMPS and VDDA18PMU can be connected to GND (internal SMPS is not used).

At minimum, we recommend:

• In External SMPS mode:

  • 2 voltage regulators (LDO or DC/DC Buck) at 1.8V (VDDA18AON direct and VDDA18 enabled by PWR_ON)

  • 2 voltage regulators (LDO or DC/DC Buck) at 3.3V (VDD direct and VDD3V3 enabled by PWR_ON)

• Internal SMPS:

  • Same configuration as External SMPS but with an additional.
    • 1 voltage regulator at 1.8V (VDDSMPS and VDDA18PMU enabled by PWR_ON)

Regarding ramp times, the only condition is exceeding the thresholds of VDD POR and VDDA18AON POR. This will activate the PWR_ON output to allow the sequence.

I hope it will help you.

Best regards,

Romain,