I am trying to use the hardware CRC built into the embedded flash module. When I use the start and end addresses and kick off the CRC, the processor halts and I have to do a full flash erase to get it back. Are the start and end addresses relative to the base of the flash bank? Here is my code:
// Unlock FLASH_CR1/2 register
FLASH->KEYR1 = 0x45670123;
FLASH->KEYR1 = 0xcdef89AB;
// Enable the CRC feature by setting CRC_EN in FLASH_CR1/2
FLASH->CR1 |= FLASH_CR_CRC_EN;
// Lock the CR1/2 register
FLASH->CR1 |= FLASH_CR_LOCK;
// Set crc burst length to 01: 64 flash words (64 * 32 bytes/word = 2048 bytes)
// In the link script, the binary must end on a 2048 byte boundary in this case
FLASH->CRCCR1 &= ~FLASH_CRCCR_CRC_BURST_Msk;
FLASH->CRCCR1 |= FLASH_CRCCR_CRC_BURST_0;
// Check CRC between defined addresses, not by sector
FLASH->CRCCR1 &= ~FLASH_CRCCR_CRC_BY_SECT;
// FLASH->CRCCR1 |= FLASH_CRCCR_CRC_BY_SECT;
// Set start and end addresses, relative to the start of this flash bank
// (i.e. address 0x8000000 is 0 on bank 1)
FLASH->CRCSADD1 &= ~FLASH_CRCSADD_CRC_START_ADDR_Msk;
FLASH->CRCSADD1 = 0;
FLASH->CRCEADD1 &= ~FLASH_CRCEADD_CRC_END_ADDR_Msk;
// FLASH->CRCEADD1 = (((uint32_t)&_ebin) - ((uint32_t)&_bflash)) & FLASH_CRCEADD_CRC_END_ADDR_Msk;
FLASH->CRCEADD1 = 0x80;
// Start CRC
FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC;
// Wait on CRC_BUSY in FLASH_SR
while(FLASH->SR1 & FLASH_SR_CRC_BUSY);
x = FLASH->SR1 & FLASH_SR_CRC_BUSY;
It halts on line 30. I've tried a number of start and end addresses.
