Hello all,
When I had a beautiful STM32U5 in hand the world was still good.
But now I have a comprehension question about the STM32L0, I have an 8-bit buffer and now the fastest way to AES decrypt/encrypt this data is via DMA with active burst mode.
To activate the burst mode on the STM32U5, we just need to set the corresponding registers with the needed value, but this is not the case on STM32L0.
Do I correctly understand, that Burst mode is only available on Timer2/3?
So that to transfer data using this mode to the AES engine, 3 DMA channels must to be configured.
DMA channel:
1. Buffer -> TIM2/3 Register (DMA Burst mode 8bit -> 32bit) for a burst mode here. (first DMA Channel)
2. TIM2/3 -> AES-IN (second DMA Channel) (32bit->32Bit)
AND to get the data out of AES
3. AES-OUT->De/Encrypted newBuffer (No burst) (third DMA Channel)(32bit->32bit)
Are these the corresponding sequences that need to be performed?
We absolutely need the burst mode to resolve the misalignment issue avoiding copying of data that consumes time and is forced to limit the data size, since a buffer must be reserved for the copy. Note that dynamic memory is not an option!
For the question: "Why do you need it at all"?
I use an 8bit buffer, but I can't always make sure that the buffer contains correct data and it won't work to say "start from position 1 or 3 of my buffer array if you let the DMA operate 32bit wise". This is because the blocks are fixed aligned.
Exactly for this there is the so called burst mode. so the DMA operation is only triggered when the desired bit size is reached. e.g. I have 8 bit but need 32bit for AES.
In this case the following will happen without burst:
The DMA shifts the first 8bit over and there are still zeros in the DMA register. these are written into the AES and the AES is triggered "0x85, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00". But this is not what you want.
So you activate the burst mode and the DMA puts the 8bit bit by bit into its own register to pass them bundled.
In the reference manual I read that the L0 uses the TIM2/TIM3 to enable burst mode, which I find a bit wild.
Therefore the question, how the procedure is. I would need then between ~3 DMA Channels only for Burst+AES or?
E.g.
Put in:
Buffer in Tim2_ch3 is DMAmux 0b1000 (DMA channel1)
from there into AES_IN would be DMAmux 0b1011(DMA channel5)
Get out:
AES_OUT with DMAMux 0b1001(DMA channel 3)
Can anybody help me ? :D
