Why is DMA reducing my pulse width?

bikejog · ‎2013-07-31

Posted on August 01, 2013 at 03:43

Howdy,

So I enabled DMA1, on STM32F103, copying two 32-bit words (set and clear PF.15) from flash to GPIOF->BSRR at 25kHz. I then run this code with all interrupts disabled

while(1) {

GPIOF->BSRR = 1 << 14;

asm(''nop'');

GPIOF->BRR = 1 << 14;

asm(''nop'');

}

The length of the high pulse on PF.14 is around 175nSecs when DMA is not active. When DMA fires and outputs a high pulse on PF.15, sometimes that pulse width of PF.14 drops to around 120nSecs. I understand that the bus matrix uses round robin scheduling and that sometimes the DMA or CPU will have to block, but I would expect that the blocking would increase a pulse length and not decrease it. What's happening here? Does this has anything to do with out of order execution and that I need to use memory barrier instructions somewhere?

TIA

Andy

#gpio-dma

bikejog · ‎2013-08-07

Posted on August 08, 2013 at 04:38

> Peripheral transactions are not reordered and are all executed, so by the time the processor receives the value from read in step 2, the register is surely written. Now the GPIO might have imposed additional delay between the register writing and actual pin change, and the instruction in 3 might got executed during waiting for the result of instruction 2, if it does not depend on it. I don't believe any of these is happening in the STM32.

Would this be one way to do a guaranteed delay after outputting a pulse? Is the DSM instruction needed?

write gpio

read gpio

dsm

delay