Why does PA4 chip select not stay high when configuring PUPDR pull-up on STM32F407VGTX?

[Ash1]

Hi,
I’m working with the STM32F407VGTX and I am using GPIO PA4 as the SPI chip-select (CS) pin. In my GPIO initialization, I set the PUPDR register to configure PA4 with a pull-up, expecting the CS pin to remain HIGH when idle. However, I observe on my logic analyzer that after initialization PA4 goes HIGH briefly, then returns LOW (its default state) even though the pull-up is set. I am attaching a screenshot of my logic analyzer for reference.

Could anyone please explain why the pin doesn’t remain high with the pull-up configuration, and what’s the correct way to configure PA4 so that CS is HIGH when SPI is not active?

Thank you!

[mƎALLEm]

Hello,

The pull-up resistor can't force a line to a high level when the line is low. The pull up can force he line high only when the line is high-Z. 

[TDK]

On the STM32F4, The SPI_NSS pin is driven low while the peripheral is enabled, regardless of if data is being sent or not. The only way to have to go low for each transaction is to turn it into a GPIO pin and control it manually.