2013-06-06 11:48 AM
Hello,
I've TIM1 set for PWM signal generation (STM32F407VG). Everything works well but I want an interrupt to be rised on the falling edge of pulse and I have no idea how to set it. Currently I've the following settings for the TIM1 IRQ: NVIC_InitStructure.NVIC_IRQChannel = TIM1_CC_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); //Attach_Tim_Interrupt(TIM1_IRQn, 0); TIM_ITConfig(TIM1, TIM_IT_CC1, ENABLE); ... ... void TIM1_CC_IRQHandler(void) //Tim1 ISR { TIM_ClearITPendingBit(TIM1, TIM_IT_CC1); ... ... } The interrupt function is rised (confirmed by breakponit) but I don't know if it is on the pulse rising edge, the falling edge or both of them. I've found the following possible setting for the TIM1 interrupt: NVIC_InitStructure.NVIC_IRQChannel = TIM1_CC_IRQn or TIM1_BRK_TIM9_IRQn or TIM1_UP_TIM10_IRQn or TIM1_TRG_COM_TIM11_IRQn and TIM_ITConfig(TIM1, TIM_IT_CC1, ENABLE) where TIM_IT_CC1 can also stand for: TIM_IT_CC2 or TIM_IT_CC3 or TIM_IT_CC4 or TIM_IT_COM or TIM_IT_Trigger or TIM_IT_Break or TIM_IT_Update Which settings should I use for the pulse falling edge interrupt? Thank you in advance for any help...2013-06-07 02:36 AM
Read the respective chapter in the User Manual first.
In the usual one-directional (upcounting or downcounting) mode, one edge of PWM is generated at the timer over/underflow (which corresponds to the Update Event (if not disabled)); the other at the respective Compare Event. Which edge is generated at which event depends on which PWM mode is chosen (and the direction of counting). You are surely aware of the latencies associated with interrupts, are you. JW PS. You could try to ask also at some of the Czech-language fora, e.g. http://mcu.cz/plugins/smf/smf.php?board=531.02013-06-10 11:23 AM