The register interface may be at HCLK, but the SYSCLK is the fastest clock (VCO pulses, and other faster source might be available), and the others are divided down from there.
Any particular reason it is critical to know? I'm not sure ST has shared more than a black-box clock tree diagram. The RCC unit is always clocked, other peripherals have gated clocks, or multiple sources.
The TIM can be provided a clock 2x the speed of the APB they are on. Not really a multiplication, but rather a clock from one divider earlier in the chain.
