STM32H747 DSI 2-Lane Mode Issues with CO5300 Display Driver

[amattes]

Hello! I am encountering some issues when trying to run 2-Lane DSI with an STM32H747.

Current Hardware Configuration:

• MCU: STM32H747 (using the Cortex-M7 core)
• Display Driver: Chipone CO5300 OLED Display Driver
• Display Panel: Round TOH143XRT-01CG2 1.43" 466×466 AMOLED
• Interface: MIPI DSI (adapted command mode)

Issue I am experiencing:

I have successfully implemented 1-lane DSI communication between the STM32H747 and CO5300 display driver. However, when I configure both the STM32 DSI host and CO5300 for 2-lane operation, the display is not responsive (black screen / nothing being displayed)

The display pipeline works as follows:

1. DMA2D → Performs 2D graphics operations and copies framebuffer data to SRAM
2. LTDC → Reads framebuffer from memory, performs layer blending, generates parallel RGB pixel stream (HSYNC, VSYNC, DE, pixel clock, RGB data)
3. DSI Wrapper → Converts LTDC parallel RGB stream into a format suitable for DSI host
4. DSI Host → Packetizes pixel data into MIPI DSI packets, serializes data through D-PHY lanes
5. CO5300 → Receives DSI packets, writes pixel data to internal GRAM, drives AMOLED panel

Configuration Details:

Clock Configuration:

• HSE: 25 MHz external crystal
• System Clock (SYSCLK): 400 MHz (via PLL1)
• AHB/APB3 Clock: 200 MHz
• DSI PLL:
• Input: HSE / 25 = 1 MHz
• PLLNDIV (N): 100
• PLLIDF (IDF): 5 (÷5)
• PLLODF (ODF): 0 (÷1)
• DSI PHY Clock: 500 MHz (100 × 25 MHz / 5)
• Lane Byte Clock: 62.5 MHz (500 MHz ÷ 8)
• LTDC Pixel Clock (PLL3R): ~38.4 MHz
• DSI TX Escape Clock Divider: 4 (for low-power mode commands, ~50 MHz / 4 = 12.5 MHz)

LTDC Configuration:

• Mode: Primary Layer Format: RGB888 
• Resolution: 466×466 pixels
• Framebuffer: Located in D2 SRAM (0x30000000), MPU configured for write-through cacheable access
• Timing Parameters:
• HSYNC: 2 clocks
• VSYNC: 2 lines
• HBP (Horizontal Back Porch): 2 clocks
• VBP (Vertical Back Porch): 2 lines
• Active Width: 466 pixels
• Active Height: 466 lines
• Total Width: 470 clocks
• Total Height: 470 lines

DSI Host Configuration:

• Mode: Adapted Command Mode (DSI->MCR CMDM bit set, DSI->WCFGR DSIM bit set)
• Virtual Channel: 0
• Color Coding: RGB888 (24-bit)
• Command Size (LCCR): 466 pixels
• Number of Lanes (PCONFR_NL):
• 1-Lane Mode: 0 (Works)
• 2-Lane Mode: 1 (Fails)
• PHY Timings (for 2-lane):
• Clock Lane HS→LP Time: 35
• Clock Lane LP→HS Time: 35
• Data Lane HS→LP Time: 35
• Data Lane LP→HS Time: 35
• Stop Wait Time: 10
• UIX4 (Unit Interval × 4): Calculated as (4000000 × IDF × (1 << ODF)) / ((HSE_VALUE / 1000) × PLLNDIV) = ~80
• Clock Lane Mode: Continuous clock enabled (CLCR_DPCC bit set)
• Low Power Commands: Enabled during initialization, disabled during refresh

DSI Initialization Sequence (2-Lane):

1. Disable DSI
2. Reset DSI wrapper
3. Configure and enable DSI PLL (wait for PLLLS lock)
4. Set TX Escape Clock divider to 4
5. Configure number of lanes: DSI->PCONFR = 1 (2 lanes)
6. Enable PHY digital section (PCTLR_DEN)
7. Enable clock lane (PCTLR_CKE)
8. Wait for stop state: Check DSI->PSR for PSS0 | PSS1 | PSSC (both data lanes + clock lane)
9. Configure UIX4 timing
10. Configure PHY HS↔LP transition timings (CLTCR, DLTCR)
11. Configure clock lane continuous mode
12. Configure adapted command mode parameters
13. Enable DSI host and wrapper
14. Start LTDC

CO5300 Configuration:

Lane Mode Register (LANESEL, 0x03):

Initialization Sequence:

1. Hardware reset via GPIO (low 10ms, high 10ms)
2. Unlock CMD2 page access (password: 0xF4=0x20, 0xF5=0xF0)
3. Switch to OLED IP page (0xFE=0x21)
4. Set lane mode: 0x03 = 0x01 (2-lane)
5. Configure display timing, gamma, power settings
6. Set memory access control (MADCTL 0x36 = 0x80)
7. Set pixel format (COLMOD 0x3A = 0x55, RGB565)
8. Set column address (CASET 0x2A): columns 6-471 (466 visible pixels with 6-pixel offset)
9. Set page address (PASET 0x2B): rows 0-465
10. Exit sleep mode (SLPOUT 0x11), wait 120ms
11. Display ON (DISPON 0x29)

Observed Symptoms in 2-Lane Mode:

1. Display remains black after initialization completes successfully OR Greenish screen appears (suggesting uninitialized framebuffer data is being transmitted)
2. Initialization sequence does not timeout - all register checks pass (PLLLS lock, PSR stop states, etc.)

What I've Verified:

• DSI PLL locks successfully (PLLLS bit set)
• PHY stop state check passes for both lanes (PSS0, PSS1, PSSC all set)
• DSI->PCONFR reads back 0x01 (2-lane mode confirmed)
• CO5300 LANESEL register written with 0x01
• Clock lane continuous mode enabled
• PHY timings configured (HS↔LP transition times)
• LTDC timing parameters unchanged between 1-lane and 2-lane modes
• Same initialization sequence works perfectly in 1-lane mode

What I've Tried:

• Configuring lane count before PHY enable
• Configuring lane count after PHY enable
• Both continuous and non-continuous clock modes
• Verified UIX4 calculation matches STM32H747-Disco Example formula
• Increased stop-state wait timeout
• Verified all DSI error registers are clear (ISR0, ISR1)

Questions:

1. Are there additional DSI wrapper or host registers that need adjustment for 2-lane mode? (Beyond PCONFR_NL)
2. Does LTDC timing need adjustment when switching from 1-lane to 2-lane DSI? (Even though LTDC timing is independent of DSI lane count)
3. Is there a specific initialization order required for 2-lane mode? (e.g., must lane count be set before or after PHY enable?)
4. Are there any known errata for STM32H747 DSI 2-lane operation?
5. Could this be a CO5300-specific issue with 2-lane initialization? (Though datasheet suggests it should work)

Any insights or suggestions would be greatly appreciated!

Thank you!   -AM