Where is TIM2_CH1 on the STM32F4 chips?

[johnjohn9105]

Posted on January 25, 2014 at 05:16

I can't find the TIM2_CH1 pin in table 7 or in table 9 of the STM32F405/407 datasheet. I did see [DEAD LINK /public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/STM32F407%20TIM2_CH1&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=185]this discussion but I'm not sure the answer is correct. Figure 134 of the reference manual shows that the ETR pin belongs to the timer, not to any of the channels inside the timer as the previous thread suggests.

Is PA0 AF1 actually TIM2_CH1 (and not TIM2_CH1_ETR as table 9 shows)? That makes the most sense to me, especially when looking at AF1 for pins PA1, PA2, and PA3, but I'd rather double check here before I lay out a board. #poor-documentation

[Tesla DeLorean]

Posted on January 25, 2014 at 06:37

I'm not sure the answer is correct.

So go get a STM32F4-DISCO or STM3240G-EVAL board and validate it, then you can be sure, and we'd have something to talk about.

[waclawek.jan]

Posted on January 25, 2014 at 12:50

The documentation is crap, and those who are trying to make changes in it make it just worse.

In the Rev.3 of said datasheet, AP1 of PA0, PA5 and PA15 are marked as ''TIM2_CH1/TIM2_ETR''. In Rev.4, PA15 is still marked the same way, while the other two are confusingly marked as ''TIM2_CH1_ETR'' (even more confusingly, this wraps as ''TIM2_CH1_E/TR)''. [EDIT] I realized why only two are changed - in the third, there's a space between ''TIM'' and rest of the label ''TIM 2_CH1''; and whoever made that stupid edit, used a search and did not care to look at the rest of the table. This IMO *is* a prime example of poor documentation skills and practices, in all three ways: incorrectly created description, unnecessarily changed, and not changed consistently. The question of shared functions arises quite often and there's no hint in the documentation on it. It would be enough to say something along the lines of  ''they are simply physically connected together'' and ''you are not supposed to use both at the same time in the given peripheral''. Even the port direction driven from peripherals (as it is with the TIM_CHx pins, for example, which is different between the model lines) is not clarified at all.   I know that writing proper documentation is a hard and expensive task and requires more than some random people hired at the minimum wage; OTOH the current state of it - that a casual reader as I am is able to find dozens of more or less serious omissions and errors, not to mention the insufficiently and misleadingly described functionality - is just a shame. And replacing proper documentation with a thin wrapper nicknamed ''peripheral library'' and a couple of handwavings is not a solution. JW

[Tesla DeLorean]

Posted on January 25, 2014 at 14:02

My response was more in the vain of ''Asked and Answered'' where asking the same question over again somehow should illicit a different response. Debating the interpretation, and dissecting the prose, is not the direction I come at this, I'm more pragmatic, and look at how things actually behave, and how logic/gates may have been implemented in silicon. In this case if you don't think an answer is correct, you go run a test and validate this alternate hypothesis.

Jan is correct, the documentation sucks pretty badly on many counts, and I too found the worsening naming scheme that first appeared in one of the F0-Discovery manuals as I recall. This is compounded by the fact that parts in different series have slightly different peripheral implementations. There are at least four different CRC peripheral implementations, and two of those are in F0 parts of different flavors. There as several design aspect of the parts which I find quite amateurish, some perhaps can be attributed to reducing gates/power, but others just seem to lack vision/ingenuity.