What is the DBATTEN Setting in UCPD_CR register

[Carl_G]

The DBATTEN setting in the UCPD_CR register claims the following 

But as far as I know, the dead battery functionality is always present. It would have to be to work unless this is stored in NVM.

Maybe this DBATTEN is some other Rd value? Maybe the ANAMODE is a proper Rd but this one is a sortof Rd light that is only sufficient to wake the MCU? I can't tell because no information is provided.

If the MCU is powered there is not really a "dead" battery condition. If the MCU is not powered this setting can't take effect.

Any ideas?

[FBL]

Dear @Carl_G 

Let me check and get back to you about DBATTEN bit. As far as I can see it impacts only G0x1 (RM0444). 

In the meantime, some insights about dead battery feature in this article could be helpful as well.

[Carl_G]

I am only using it with G071. It does not seem to do anything I can tell. I can imagine that maybe its a low power version of Rd that you can use in STOP mode but other than that I can't imagine what it could be. I'll check the resistance if I get a chance.

[FBL]

Hi @Carl_G 

1. Why is there a DBATTEN bit if dead battery function is hardware-based?
   The hardware dead battery function works via the DBCC pin even when unpowered. DBATTEN lets software disable this hardware mode after power-up. Now, to explain the background, the first STM32G0 generation used DBATTEN and STROBE to extend dead battery behavior into STANDBY, by maintaining the STROBE latch even when VDDCORE (and thus UCPD) is OFF. In newer STM32 families, this was replaced by dedicated bit DBDIS powered by a separate 3.3V supply that stays ON in standby, simplifying dead battery control.

2. How can DBATTEN affect dead battery behavior if MCU is off?
   The DBCC pin controls the pull-down MOSFET regardless of power. Writing the STROBE bit latches DBATTEN and can disable hardware dead battery mode, handing control to software.

3. Does DBATTEN control a different or weaker Rd resistor than ANAMODE?
   No, there is only one Rd resistor. It has ±20% tolerance unpowered (per spec) and is trimmed to ±10% after power-up for better accuracy.

4. Is dead battery function dependent on external circuitry despite DBATTEN?
   Dead battery mode relies mainly on internal hardware via DBCC and DBATTEN. The initial DBATTEN disable only takes effect after STROBE; before that, dead battery mode is enabled by default.