on 2024-09-08 05:00 AM
Dead battery configuration control (DBCCx) pins play a crucial role in USB Type-C® applications to manage scenarios where the device's main power source is unavailable (dead battery). These pins, used with configuration channel (CC) pins, help the device to be detected and powered by a connected power source. Therefore, this FAQ article covers the dead battery feature whenever it is implemented in an STM32 MCU.
This block resumes the pinout of the UCPD digital controller and the possible connections are detailed in the corresponding datasheet.
For dead battery support, the DBCC pins (UCPDx_DBCC1 and UCPDx_DBCC2) must be externally connected to their respective CC pins (UCPDx_CC1 and UCPDx_CC2). This connection allows the internal pull-down resistor to signal a VBUS supply request when the device is unpowered.
If dead battery support is not required (for example, for source-only products), the DBCC pins (UCPDx_DBCC1 and UCPDx_DBCC2) must be tied to ground. This prevents the activation of the internal pull-down resistors, allowing the pins to be used for other functions.
The dead battery pull-down resistor on UCPD pins can be disabled by setting the UCPD_DBDIS bit in the PWR_CR3 register for STM32G4 for instance. Dead battery disabling is usually performed by our USB PD stack through HAL_PWREx_DisableUCPDDeadBattery();
This action is performed after the startup sequence, allowing the pins to be used for other functions.
The internal pull-down resistor value for UCPD pins is 5.1kΩ. This ensures that the device can signal a VBUS supply request when unpowered.
Yes, but these pins have unique characteristics (FT_d or FT_c). When the device is used as a USB Type-C® source or sink without dead battery support, the DBCC pins can be used as GPIOs. You need to ensure that these pins are tied to ground to disable the dead battery pull-down resistors. The design of these IOs is different mainly we have to sustain 5 V when there is no power supply. So, they present more leakage than standard GPIOs.
UCPD peripheral controls these resistors via ANAMODE and ANASUBMODE[1:0]. Typically, configuration of these registers in handled in USB PD stack. If only one of the CC lines is needed, you can disable control on the other line through the CCENABLE[1:0] bitfield or LL_UCPD_SetccEnable() when initializing cable detection in CAD_Init().
Check coding for ANAMODE, ANASUBMODE, and link with TYPEC_VSTATE_CCx in the corresponding reference manual.
When the MCU is unpowered, it still presents the “dead battery” Rd, provided that UCPDx_DBCC1 and UCPDx_DBCC2 pins are each connected to UCPDx_CC1 and UCPDx_CC2 pins, respectively. If dead battery behavior is not required, tie UCPDx_DBCC1 and UCPDx_DBCC2 pins to ground.
For applications that do not use the UCPD peripheral, it is recommended to disable the internal pull-down resistor Rd at startup. This is done through the strobe bits in SYSCFG registers as explained in corresponding reference manual.
The following section lists the principal topologies of USB Type-C® applications with the dead battery feature as detailed in table 12 in AN5225:
Use case |
Pros |
Cons |
1. VBUS-powered sink (dead battery) |
Dead battery support, seamless operation |
Complexity, power consumption |
2. Sink without dead battery support |
Simplicity, lower power consumption |
Limited functionality, manual intervention |
3. Protected sink with dead battery |
Enhanced protection, dead battery support, seamless transition |
Increased complexity, higher cost |
4. Protected sink without dead battery |
Enhanced protection, simplicity |
Limited functionality, manual intervention |
Understanding the proper configuration and management of DBCC pins in USB Type-C® devices is crucial for ensuring seamless power delivery and communication, especially in scenarios where the device's main power source is unavailable.
For further technical specifications, always refer to the corresponding datasheets and reference manuals and check section 11.3.1 DBCC1 and DBCC2 lines in AN5225.
Caution: User should be aware of differences in output timing, speed, and leakage for FT_c FT_d GPIOs compared to standard GPIOs.