Posted on September 22, 2014 at 12:38I want to direct drive a rgb tft display via FSMC/DMA and an external async sram as framebuffer. The cpu is a STM32F103ZC.
What happens when CPU writes between transfers to RAM?
The transfers would be then: DMA Read (FSMC SRAM), DMA Write (FSMC TFT), CPU Write (FSMC SRAM).
I have read that there is a round robin scheduler. How much bandwidth can CPU get in this case?
