Understanding FSMC arbitration
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2014-09-22 3:38 AM
Posted on September 22, 2014 at 12:38
I want to direct drive a rgb tft display via FSMC/DMA and an external async sram as framebuffer. The cpu is a STM32F103ZC.
What happens when CPU writes between transfers to RAM? The transfers would be then: DMA Read (FSMC SRAM), DMA Write (FSMC TFT), CPU Write (FSMC SRAM). I have read that there is a round robin scheduler. How much bandwidth can CPU get in this case?
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2014-09-22 4:03 AM
Posted on September 22, 2014 at 13:03
You should read AN2548. Beyond what's given there, you are left to experimentation, I am afraid.
JW