underclocking STM32F030

[lukas239955_stm1_st]

Posted on November 04, 2014 at 13:17

I have problem when underclocking STM32F030.

When I setup to RCC->

CFGR2  

higher value than RCC_CFGR2_PREDIV1_DIV4 (for example DIV5 - DIV16)

then PLL is never ready ( RCC_CR_PLLRDY ) With value <= RCC_CFGR2_PREDIV1_DIV4    its OK and works. Where could be an issue?

[waclawek.jan]

Posted on November 04, 2014 at 13:29

Ahoj Lukas,

Note, that the PLL input clock must not fall below 1MHz - see Table 36 in STM32F030 datasheet. JW

[lukas239955_stm1_st]

Posted on November 04, 2014 at 13:45

Thanks for reply.

Yes, I want to get run <1 - 2>MHz. I have external 8MHz XTAL so I expect setup prediv more than 4. Or it will be better to change XTAL to 1MHz and run without PLL?  I expext, that there will no limits when underclocking, but at the output of multiplier must be frequency higher than 16MHz

[Tesla DeLorean]

Posted on November 04, 2014 at 20:46

The 1 -24 MHz input range seems rather broad, most of ST's other designs have tighter ranges for the PLL comparison frequencies. The minimum PLL output is specified as 16 MHz

If you want to run the part slowly, why not just use the HSE, and the AHB/APB dividers?

[waclawek.jan]

Posted on November 04, 2014 at 21:36

> The 1 -24 MHz input range seems rather broad, most of ST's other designs have tighter ranges for the PLL comparison frequencies.

The newer ranges appear to have a different PLL. For example, the PLL in 'L05x is specified for 2-24MHz input.

> If you want to run the part slowly, why not just use the HSE, and the AHB/APB dividers?

+1 > Yes, I want to get run <1 - 2>MHz. > I have external 8MHz XTAL so I expect setup prediv more than 4. That should work, according to the datasheet/RM, provided the PLL output is expected to be above 16MHz. I honestly don't know why it would not work. Post a minimal but complete code exhibiting the problem. If I guessed correctly and you speak Czech or Slovak, try to ask at our local mailing list list.hw.cz . JW

[Tesla DeLorean]

Posted on November 04, 2014 at 21:51

It does also state it's ''designed'' to work but is not tested, which means something like ''all the gears should have the right number of teeth, but we don't try all combinations of shifter settings on the test track'', or more dangerously that they have only characterized the nominal settings.

Looking at the internal clocks via MCO (PA8) might be enlightening as to what exactly is going on, or at least rule in/out particular hypothesis.

[lukas239955_stm1_st]

Posted on November 05, 2014 at 14:41

Yes that was my fault of non correct settings of output multiplier. It doest pass into datasheet limits for PLL output.