Posted on November 04, 2014 at 13:17I have problem when underclocking STM32F030. When I setup to RCC->CFGR2 higher value than RCC_CFGR2_PREDIV1_DIV4 (for example DIV5 - DIV16) then PLL is never ready ( RCC_CR_PLLRDY ) With value <= RCC_CFGR2_PRE...
Posted on November 05, 2014 at 14:41Yes that was my fault of non correct settings of output multiplier. It doest pass into datasheet limits for PLL output.
Posted on November 04, 2014 at 13:45Thanks for reply. Yes, I want to get run <1 - 2>MHz. I have external 8MHz XTAL so I expect setup prediv more than 4. Or it will be better to change XTAL to 1MHz and run without PLL? I expext, that there will no l...
