Trigger interrupts for ETR

gor · ‎2014-05-18

Posted on May 18, 2014 at 14:10

Hi!

(Using the STM32F103RBT6 chip)

I've configured TIM2 timer as a prescaler for TIM3 (RM0008 page 386).

Timer TIM2 is configured for ETR (RM0008 page 365).

So what I've got is a 32bit timer counting pulses on PA0 (successfully working).

Now I want to get an interrupt on the rising edge of the pulses that fed to ETR

pin while I count them (TGI interrupt as shown on RM0008 page 352 figure 100).

When I configure TIM2 for trigger interrupt:

TIM_ITConfig(TIM2, TIM_IT_Trigger, ENABLE);

Nothing happens, but if I configure it for Update interrupt as:

TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);

I'm actually getting the Update interrupt as it should.

Am I missing something?

Thanks,

Alexey

waclawek.jan · ‎2014-05-19

Posted on May 19, 2014 at 09:20

And do you have ETR used as trigger at all, i.e. do you use external clock mode 1 or 2? Show us the content of TIM2->SMCR.

JW

gor · ‎2014-05-19

Posted on May 19, 2014 at 13:18

I use ETR(mode 2), at runtime the TIM2->SMCR value is 0x4000.

TIM2->SMCR is initialized in the code below..

Then I apply a 790kHz 3.3Vpp square wave to pin PA0 for testing..

(same effect on lower frequencies as well.. 1Hz, 10Hz, 100Hz etc'.. )

RTC is used with 1 second interrupt to generate a 1 second timebase to read

the frequency.

I get the correct frequency in the ''Frequency'' variable.

If instead of the trigger interrupt I use the update interrupt(just uncomment/comment in the code below)

I get the counter counting same as MSB variable (which is just TIM3->CNT) as expected.

But if I try to interrupt on trigger, I get nothing(It doesn't enter the interrupt at all)..

(I expect the trigger interrupt at each rising edge on PA0 but it doesn't happen..)

This is my code:

#include ''stm32f10x.h''

#include ''stm32f10x_gpio.h''

#include ''stm32f10x_rcc.h''

#include ''stm32f10x_tim.h''

#include <stdio.h>

uint16_t MSB = 0;

uint16_t LSB = 0;

uint32_t counter = 0;

uint32_t counted = 0;

uint32_t Frequency = 0;

void RTC_init();

int main(void)

{

RTC_init();

// configure PA0 pin

GPIO_InitTypeDef GPIO_InitStructure;

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;

GPIO_Init(GPIOA, &GPIO_InitStructure);

// enable clocking of GPIOA and timers

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);

RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);

RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);

RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);

// set periods

TIM2->ARR = 65535; //set period

TIM3->ARR = 65535; //set period

/*

TIM2->CR1 = (TIM2->CR1 & ~((uint16_t)(0x3 << 8))) | ((uint16_t)(0x00 << 8)); // set CKD[1:0]=00 => tDTS = tCK_INT

TIM2->CR1 = (TIM2->CR1 & ~((uint16_t)(0x1 << 4))) | ((uint16_t)(0x0 << 4)); // set DIR=0

TIM3->CR1 = (TIM3->CR1 & ~((uint16_t)(0x3 << 8))) | ((uint16_t)(0x00 << 8)); // set CKD[1:0]=00 => tDTS = tCK_INT

TIM3->CR1 = (TIM3->CR1 & ~((uint16_t)(0x1 << 4))) | ((uint16_t)(0x0 << 4)); // set DIR=0

*/

// set TIM2 to ETR according to RM0008 page 365.

TIM2->SMCR = (TIM2->SMCR & ~((uint16_t)(0xF << 8))) | ((uint16_t)(0x0000 << 8)); // set ETF=0000

//TIM2->SMCR = (TIM2->SMCR & ~((uint16_t)(0x3 << 12))) | ((uint16_t)(0x1 << 12)); // set ETPS=01 (/2)

TIM2->SMCR = (TIM2->SMCR & ~((uint16_t)(0x3 << 12))) | ((uint16_t)(0x0 << 12)); // set ETPS=00

TIM2->SMCR = (TIM2->SMCR & ~((uint16_t)(0x1 << 15))) | ((uint16_t)(0x0 << 15)); // set ETP=0

TIM2->SMCR = (TIM2->SMCR & ~((uint16_t)(0x1 << 14))) | ((uint16_t)(0x1 << 14)); // set ECE=1

// set TIM2 as prescaler for TIM3 to get 32bit timer (RM0008 page 386).

TIM2->CR2 = (TIM2->CR2 & ~((uint16_t)(0x7 << 4))) | ((uint16_t)(0x2 << 4)); // set MMS=010

TIM3->SMCR = (TIM3->SMCR & ~((uint16_t)(0x7 << 4))) | ((uint16_t)(0x1 << 4)); // set TS=001

TIM3->SMCR = (TIM3->SMCR & ~((uint16_t)(0x7 << 0))) | ((uint16_t)(0x7 << 0)); // set SMS=111

// enable TIM2, TIM3

TIM2->CR1 |= (uint16_t)0x1;

TIM3->CR1 |= (uint16_t)0x1;

// enable interrupt on TIM2 triggering (TGI interrupt as shown on RM0008 page 352 figure 100)

//TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);

TIM_ITConfig(TIM2, TIM_IT_Trigger, ENABLE);

// enable interrupts from TIM2

NVIC_EnableIRQ(TIM2_IRQn);

while (1)

{

}

extern ''C'' void TIM2_IRQHandler(void)

{

//if (TIM_GetITStatus(TIM2, TIM_IT_Update) == SET)

if(TIM_GetITStatus(TIM2, TIM_IT_Trigger) == SET)

{

//TIM_ClearITPendingBit(TIM2, TIM_IT_Update);

TIM_ClearITPendingBit(TIM2, TIM_IT_Trigger);

counter++;

}

extern ''C'' void RTC_IRQHandler(void)

{

if (RTC_GetITStatus(RTC_IT_SEC) != RESET)

{

RTC_ClearITPendingBit(RTC_IT_SEC);

LSB = TIM2->CNT;

MSB = TIM3->CNT;

TIM2->CNT = 0;

TIM3->CNT = 0;

Frequency = (uint32_t)(((uint32_t)MSB << 16) | LSB);

counted = counter;

counter = 0;

RTC_WaitForLastTask();

}

void RTC_init()

{

NVIC_InitTypeDef NVIC_InitStructure;

NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);

NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn;

NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;

NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;

NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;

NVIC_Init(&NVIC_InitStructure);

RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);

PWR_BackupAccessCmd(ENABLE);

BKP_DeInit();

RCC_LSEConfig(RCC_LSE_ON);

while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)

{}

RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);

RCC_RTCCLKCmd(ENABLE);

RTC_WaitForSynchro();

RTC_WaitForLastTask();

RTC_ITConfig(RTC_IT_SEC, ENABLE);

RTC_WaitForLastTask();

RTC_SetPrescaler(32767);

RTC_WaitForLastTask();

}

waclawek.jan · ‎2014-05-19

Posted on May 19, 2014 at 14:08

> I use ETR(mode 2), at runtime the TIM2->SMCR value is 0x4000.

That means, that ETR is not routed to TRGI, thus it can't fire the trigger interrupt.

Read the TIMx_SMCR description in RM0008, focus on the TS bitfield.

As an aside, I'd recommend not to mix the ''library'' and direct register access. Stick to one of them (I personally prefer direct register access, and use the symbolic names for bits defined in the stm32f****.h header).

JW