2014-03-09 12:46 PM
Greetings all, I'm new here so I hope I'm doing this right.
STM32F0I'm trying to trigger a DMA transfer from TIM2 with CCR1Here's my code for the timer portionTIM_TimeBaseInitTypeDef timerInitStructure;timerInitStructure.TIM_Prescaler = 0;timerInitStructure.TIM_CounterMode = TIM_CounterMode_Up;timerInitStructure.TIM_Period = 60;timerInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;timerInitStructure.TIM_RepetitionCounter = 0;TIM_TimeBaseInit(TIM2, &timerInitStructure);TIM_OCInitTypeDef outputChannelInit;outputChannelInit.TIM_OCMode = TIM_OCMode_Timing;outputChannelInit.TIM_OutputState = TIM_OutputState_Enable;outputChannelInit.TIM_OCPolarity = TIM_OCPolarity_High;outputChannelInit.TIM_Pulse = 41;TIM_OC1Init(TIM2, &outputChannelInit);TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Enable);TIM2->DIER |= (0x01 << 14) | (0x01 << 9);TIM_Cmd(TIM2, ENABLE);So what I was looking for was being about to trigger a DMA transfer when the count register reaches 41 on DMA1_Channel5.I can verify that a transfer is happening but it looks like it's happening on Update.Thanks!-Jason2014-03-10 02:41 PM
GPIO_InitTypeDef GPIO_InitStructure;
TIM_OCInitTypeDef TIM_OCInitStructure;
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
// PA1 - TIM2_CH2
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_2); // PA1 - TIM2_CH2
..
/* Output Compare Toggle Mode configuration: Channel2 */
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Toggle;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_Pulse = 14; // Same as CH1 triggering DMA to GPIOB PB[0..2]
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
TIM_OC2Init(TIM2, &TIM_OCInitStructure);
TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Disable);
// Observe phase relationship between TIM2_CH2 EDGEs on PA1 with respect to data latched to GPIOB PB[0..2]. Should be the latency of the DMA servicing
// Suggest DMA table contains 0,1,2,3,4,5,6,7 sequence looped (circular)