Posted on May 17, 2011 at 13:40Well, I found my answer - In the datasheet of course.
Here are the mappings.
FSMC_A19 TRACED0
FSMC_A20 TRACED1
FSMC_A21 TRACED2
FSMC_A22 TRACED3
FSMC_A23 TRACECLK
This was an unfortunate choice for pin mapping on ST's part. If order of trace pin mappings had been reversed, then additional address lines could have been used while preserving some level of synchronous trace debugging. Here is an example:
FSMC_19 TRACED3
FSMC_20 TRACED2
FSMC_21 TRACED1
FSMC_22 TRACED0
FSMC_23 TRACECLK
In this example, if single data line trace debugging was desired, then FSMC_A23 and FSMC_A22 would be taken for trace lines, but FSMC_A0-A21 would be free for external memory. Likewise if two data line trace debugging was desired, the FSMC_A23,A22,A21 would be used for trace lines, but FSMC_A0-A20 would be free for external memory.
Alas, this is not the case. As soon as synchronous trace debugging is selected, FSMC_A19-A23 are now unusable as address lines (for any trace debugging width).
From: helton.gregory
Posted: Tuesday, February 16, 2010 6:05 PM
Subject: Trace debugging and FSMC address lines
The answer from ST is ''No''. Trace lines cannot be shared with FSMC lines.
However, a new question comes to mind. There are reduced synchronous trace data width modes (1,2,4 bits). If only two trace bits are used, can the other FSMC line be used for external memory ? Do the trace pins map in such a manner to make this possible ?
A new request has been sent to ST for the answers. Answer will be posted here.
