Tips for custom bootloader/application?

[Dave Jones]

Posted on May 17, 2017 at 19:55

I'm new to STM32, though I've programmed other micros for decades. I'm doing my first project with an STM32L4 and need to create a custom bootloader in lower flash and an application in upper flash. I've done this before with PIC24 parts where I created 2 projects, one for the bootloader and one for the application, each with a custom linker script that forced the linker to keep them within their specific areas of flash. The bootloader set the config fuses and was burned in by the programming cable. The application was installed via a uSD card. It had to be built using identical config fuses because it didn't actually set them when installed, since it was the bootloader that simply placed the application into a portion of flash.

I'm assuming I would do something very similar here.

1 - are linker scripts tool specific? I'm using 'System Workbench' (SW4STM32). How do I find out about modifying the linker script for my needs?

2 - is there any example code of in-chip flash programming available for the STM32L4?

3 - if I understand it correctly, it's possible for the application code to move the interrupt table to RAM and use it from there? (since it can't use the interrupt table from the custom bootloader) Is this true? Anything special I need to know about doing that?

Thanks,

[Tesla DeLorean]

Posted on May 17, 2017 at 20:10

1 - GNU Linker Scripts are different from Keil Scatter Files, perform a similar job of describing memory placement to linker. ie Boot at the beginning of FLASH, App 0x4000 (or whatever) deeper. Adjust the base/size of the regions to match needs. Look at some examples, read documentation, repeat.

2 - Look at IAP examples ST provides for several of the families, process all very similar

3 - The L4 uses a Cortex-M4 this has a SCB->VTOR register that points at your current vector table, this can be in FLASH and point at either the Boot Loader, or App, etc. The Cortex-M0 lacks this register, requiring a copy to RAM, and mapping RAM to the zero address space.

Joseph Yiu has books on Cortex-Mx parts, reading these and the ARM TRM's, will help provide context.

[waclawek.jan]

Posted on May 17, 2017 at 20:16

1 - are linker scripts tool specific? I'm using 'System Workbench' (SW4STM32). How do I find out about modifying the linker script for my needs?

SW4STM32 is gcc+Eclipse. I expect the linker script to be fairly standard gcc/GNU-ld stuff, but the IDE might get into way with generating it based on some clickey stuff (I don't know for sure, I wouldn't touch any eclipsoid with a stick).

2 - is there any example code of in-chip flash programming available for the STM32L4?

The 'official' examples are Cube-based and come bundled with Cube, e.g.  [STM32Cube_FW_L4_V1.5.0\Projects\STM32L476G_EVAL\Applications\IAP\ . It may be fine if you intend to stick to Cube (thus being doomed to use whatever is in there), but extracting the real stuff out of it may be a PITA given Cubes tangled 'structure'. OTOH, flash programming itself is relatively simple to be pulled off using first principles.

3 - if I understand it correctly, it's possible for the application code to move the interrupt table to RAM and use it from there? (since it can't use the interrupt table from the custom bootloader) Is this true? Anything special I need to know about doing that?

In Cortex-M3/M4/M7, the vector table is relocatable to any address subject to an alignment boundary, a power of 2 I don't remember exactly. See PM0214, 4.4.4  Vector table offset register (VTOR).

JW

[Dave Jones]

Posted on May 18, 2017 at 06:27

>> See PM0214, 4.4.4  Vector table offset register (VTOR).

Thanks, that helps a lot. I looked up the NVIC in the datasheet for the 32L4 part I am looking at and it didn't give much info, but did say for more info on the NVIC to refer to that same PM0214. So I guess the L4 follows the same rules as the M4 as far as NVIC.

And based on what is in there, I see that the vector table can be moved to RAM or to Flash, which is great, since it can then be a vector table created in the flash of the application that I install in upper flash. And then the table points to it's new table as the application is run.

[waclawek.jan]

Posted on May 18, 2017 at 09:02

Welome to the ARM world. If you don't want just to play on the surface, you'll need to go all the way across to the architectural documents, starting with PM0214, and ultimately resorting to ARM's own Cortex-Mx Technical Reference Manual and ARMv7 ARM® v7-M Architecture Reference Manual.

You'd normally resort to vectors in RAM (together with the ISRs) only if you want to run interrupts while FLASH is unavailable (being programmed in a single-bank device, which is the majority of not-the-largest-FLASH devices) (and, as Clive said above, in Cortex-M0/M0+ where vector relocation is not available, as those are ARM v6).

JW