We're using a STM32H747IGT6 and using hardware semaphores to coordinate between the two cores.
On the CM4 I've set up TIMER3 to run at full blast:
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3);
LL_TIM_SetPrescaler(TIM3, 0); // Count at system clock
LL_TIM_SetAutoReload(TIM3, 0xFFFF);
LL_TIM_EnableARRPreload(TIM3);
LL_TIM_SetCounterMode(TIM3, LL_TIM_COUNTERMODE_UP);
LL_TIM_SetClockDivision(TIM3, LL_TIM_CLOCKDIVISION_DIV1);
LL_TIM_EnableCounter(TIM3);
I believe that means the timer is running at 240 MHz (do you agree?) which is one tick every 4.166 nsec.
So now I grab and release a hardware semaphore that is not used anywhere else in the code:
start_timer = LL_TIM_GetCounter(TIM3);
WRITE_REG(HSEM->R[TEST_SEMAPHORE_NUMBER], (HSEM_R_LOCK | LL_HSEM_COREID | SHMEM_CM4_PID));
uint32_t readBack = HSEM->R[TEST_SEMAPHORE_NUMBER];
if (readBack == (HSEM_R_LOCK | LL_HSEM_COREID | SHMEM_CM4_PID))
WRITE_REG(HSEM->R[TEST_SEMAPHORE_NUMBER], (LL_HSEM_COREID | SHMEM_CM4_PID));
end_timer = LL_TIM_GetCounter(TIM3);
delta_timer = end_timer - start_timer;
and inspect the value of 'delta_timer'. What I see is that it often takes 84 ticks (350 ns) but on occasion takes as many as 232 (967 ns).
Why does it sometimes take 3x longer, since no other process in the system is using that hardware semaphore? Can the HSEM only think about one semaphore at a time, and some other semaphore is being processed?
