TIMER1_DMA Capture

[surender2525]

Posted on March 07, 2016 at 12:25

Hi,

   I'm using STM32F103RC controller, trying to Capture Frequency from 1.2Khz to 72Mhz by using Timer-1 with DMA Channel-2. i'm not able to capture a constant count from TIM1->CCR1, the count value keeps on varying. In need of HELP.! #include ''stm32f10x.h'' #define CFGR_REG_VAL     0x001D8402;  #define System_CoreClock    72000000.0 void RCC_Configuration(void); void Timer1_Master(void); void GPIO_initailization(void); void DMA1_Channel2_configuration(void); unsigned short Memory[50]; main() { RCC_Configuration(); Timer1_Master(); GPIO_initailization(); DMA1_Channel2_configuration(); while(1); } /////////////////////////////CLOCK/////////////////////////////////////////// void RCC_Configuration(void) { RCC->CSR  |=  0x01000000; RCC->CR    =  0x00010080; //external highe speed clock enabled if ((RCC->CR & RCC_CR_HSEON))  {                 // if HSE enabled while ((RCC->CR & RCC_CR_HSERDY)==0 ); // Wait for HSERDY = 1 (HSE is ready)   //Flash access control reg FLASH->ACR =  0x12 ; //prefetch buffer enabled and flash latency(2 wait state) RCC->CFGR  =  CFGR_REG_VAL ; RCC->CR   |=  0x01000000;   //PLL enable   if (RCC->CR & RCC_CR_PLLON)    {                 // if PLL enabled     while ((RCC->CR & RCC_CR_PLLRDY) == 0); // Wait for PLLRDY = 1 (PLL is ready)   } while ((RCC->CFGR & 0x0000008) ==0); }       }  void GPIO_initailization(void) {    RCC->APB2ENR |= 0x00000001;        /**** enable afio ******/ RCC->APB2ENR |= 0x0000000C;       /**** enable gpio A & B ******/ GPIOA->CRH     = 0x00000004;       /* TIMER 1 PIN 41 FOR capture INPUT  floating*/ } //////////////////////////////TIMER1///////////////////////////////// void Timer1_Master(void)    {  RCC->APB2ENR |= 0x0800; // clock of TIM1 TIM1->PSC = 0x0000; // PSC = 1 (i.e 72MHZ/1) TIM1->ARR = 0xffff; // Autoreload value (65535) TIM1->CNT = 0x0000; // Counter value   TIM1->EGR = 0X0002; // Counter is captured in TIMx_CCR1 register TIM1->CCMR1 = 0x0031; // 01: CC1 channel is configured as input, IC1 is mapped on TI1 0011: fSAMPLING=fCK_INT, N=8 TIM1->CR2 = 0x0008; // 1: CCx DMA requests sent when update event occurs TIM1->DIER = 0x0200; // Capture/Compare 1 interrupt enable, Capture/Compare 1 DMA request enable TIM1->CR1 = 0x0001; // 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.URS bit is eanbled TIM1->CCER = 0x0001; // Capture/Compare 1 input enable }  void DMA1_Channel2_configuration(void) {     RCC->AHBENR = (RCC->AHBENR & 0xFFFFFFF6) | 0x00000001;// DMA1 clk enable DMA1_Channel2->CPAR = (int)&TIM1->CCR1; // PERIPHERAL address DMA1_Channel2->CMAR = (int)&Memory;                          // memory address DMA1_Channel2->CNDTR = 50;   // number of data DMA1_Channel2->CCR = (0xFFEF & DMA1_Channel2->CCR) | 0x00 ; //  read from peripheral  DMA1_Channel2->CCR = (0xFFDF & DMA1_Channel2->CCR) | 0x20 ;        //   circular mode enable DMA1_Channel2->CCR = (0xFF7F & DMA1_Channel2->CCR) | 0x80 ;       //   memory inc mode DMA1_Channel2->CCR |= 0x200; // high priority level DMA1_Channel2->CCR |= 0x500;   //peripheral size 16-bits and memory size 16-bits DMA1_Channel2->CCR |= 0x01;                                        // channel enable }

[Tesla DeLorean]

Posted on March 07, 2016 at 19:03

Well Input Capture just copies the value in TIMx->CNT into TIMx->CCRx, the counting element ticks at the rate of the timer described by the time base.

Typically you'd take TWO measurements and subtract them from each other to get a delta count in the ticks of the time base clock.ie a 50 Hz signal might report 10000, then 30000, then 50000, ie a delta of 20000 ticks of a clock of 1 MHz (1 us)20000us = 20ms = 0.02s, 1/50 = 0.02 sIf you want the counter to reset you'd need to use PWM Input mode.

[surender2525]

Posted on March 08, 2016 at 10:53 The original post was too long to process during our migration. Please click on the provided URL to read the original post. https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I6pU&d=%2Fa%2F0X0000000bwN%2Fu7l5HQ7Q_nNQD.Hr4Xn85KW5qOCyXJ7_qXEiCtkXfCk&asPdf=false

[surender2525]

Posted on March 08, 2016 at 12:01 ________________ Attachments : TIMER_IRQ_capture.bmp : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HzWx&d=%2Fa%2F0X0000000bO1%2FFIjOyFsAImJvB1kwhMU9UcZeN1qNqXM0I96UYJ01Y1c&asPdf=false

[Tesla DeLorean]

Posted on March 08, 2016 at 15:21

But, i'm not able to capture the same Count in DMA.!

Well the DMA can read TIM1->CCR1, it can't write TIM1->CNT = 0, so it's not going to do the same thing, is it? Also don't use the ' TIM1->SR &= ' form, just write the mask to clear the interrupt. Review the use of PWM Input mode

[surender2525]

Posted on March 09, 2016 at 11:26

PWM INPUT MODE

Thanks a lot ''Clive1''. It was verymuch Helpful.Now, It capture's the Constant count by using

PWM INPUT MODE

in Timer1 DMA..Another Doubt,Can we Cascade 2 Timers ( i.e Timer-1 Master cascade with Timer-2 Slave) and Capture Frequency from 0 to 50Mhz using DMA?I've used Timer IRQ. To get the Capture Count in IRQ,were MSB value in Timer 1 TIM1->CCR1; and LSB value in Timer 2 TIM2->CNT; )That is,Frequency Count =  TIM1->CCR1 +  (TIM2->CNT*65535);But in DMA1_Channel2->CPAR,  if we use 2 Timers, which PERIPHERAL dress should be given?

[surender2525]

Posted on March 09, 2016 at 11:30

PWM INPUT MODE

Thanks a lot ''Clive1''. It was verymuch Helpful.Now, It capture's the Constant count by using

PWM INPUT MODE

in Timer1 DMA..Another Doubt,Can we Cascade 2 Timers ( i.e Timer-1 Master cascade with Timer-2 Slave) and Capture Frequency from 0 to 50Mhz using DMA?I've used Timer IRQ. To get the Capture Count in IRQ,were MSB value in Timer 1 TIM1->CCR1; and LSB value in Timer 2 TIM2->CNT; )That is,Frequency Count =  TIM1->CCR1 +  (TIM2->CNT*65535);But in DMA1_Channel2->CPAR,  if we use 2 Timers, which PERIPHERAL dress should be given?