Timer in TIM_OCMODE_ACTIVE is always HIGH

smrtkai · ‎2017-02-15

Posted on February 15, 2017 at 15:07

Hi,

I want to generate a square wave using Timer mode TIM_OCMODE_ACTIVE. I have generated the code using STM32CubeMX and I am using a STM32F429I Discovery Board.

The output pin is always 'HIGH'. For TIM_OCMODE_INACTIVE the pin is always 'LOW'.

Changing to TIM_OCMODE_TOGGLE the ouput pin changes states. I am expecting changes on the output pin for the other modes as well. What am I doing wrong in the other modes? My configuration looks like this.

Thanks in advance.

void MX_TIM1_Init(void)

{

TIM_MasterConfigTypeDef sMasterConfig;

TIM_OC_InitTypeDef sConfigOC;

TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig;

htim1.Instance = TIM1;

htim1.Init.Prescaler = 10;

htim1.Init.CounterMode = TIM_COUNTERMODE_UP;

htim1.Init.Period = 10;

htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;

htim1.Init.RepetitionCounter = 0;

if (HAL_TIM_OC_Init(&htim1) != HAL_OK)

{

Error_Handler();

}

sMasterConfig.MasterOutputTrigger = TIM_TRGO_ENABLE;

sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE;

if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)

{

Error_Handler();

}

sConfigOC.OCMode =

TIM_OCMODE_ACTIVE

;

sConfigOC.Pulse = 0;

sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;

sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;

sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;

sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;

sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;

if (HAL_TIM_OC_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)

{

Error_Handler();

}

...

}

#tim

smrtkai · ‎2017-02-17

Posted on February 17, 2017 at 12:26

In the STM32CubeF4 Firmware I have found an example of how to use a timer with OCActive. Unfortunately there is no example for my discovery board. So I have tried to port the following code.

'STM32Cube\Repository\STM32Cube_FW_F4_V1.14.0\Projects\STM324x9I_EVAL\Examples\TIM\TIM_OCActive'

Same result: TIM_OCMODE_TOGGLE works, TIM_OCMODE_ACTIVE does not.

Does anyone have a working example for the STM32F429I-DISCO with a timer using OCMode=

TIM_OCMODE_ACTIVE?

waclawek.jan · ‎2017-02-17

Posted on February 17, 2017 at 12:56

This is the expected behaviour.

Read the description of OC1M in TIMx_CCMR1 in RM0090.

JW

smrtkai · ‎2017-02-20

Posted on February 20, 2017 at 09:20

Actually, I have done that.

The manual says:

'OC1M: Output Compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.

000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base).

001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).

010: Set channel 1 to inactive level on match. OC1REF signal is forced'

Having read that, I would expect a different behaviour than the described behaviour above. Additionally the readme of the example for

STM324x9I_EVAL states the following:

' - Connect the following pins to an oscilloscope to monitor the different waveforms:

- Use LED1 connected to PG.06 (Reference)

- PC.06 (TIM3_CH1)

- PC.07 (TIM3_CH2)

- PC.08 (TIM3_CH3)

- PC.09 (TIM3_CH4)'

So there are supposed to be changes on the output pin.

Basically, I want the timer output to get high for one cycle when TIMx_CNT=TIMx_CCR1. It's probably very simple, but I am failing on that.

waclawek.jan · ‎2017-02-20

Posted on February 20, 2017 at 23:52

I understand the point, but while the description of the OCxM=0b001/0b010 modes may be confusing, they do not produce the one-clock-wide pulse you expected.

And I also don't know of any simple way to achieve that with the STM32 timers. You of course can set the compare register to just above 0 or just below ARR and with an appropriate PWM mode achieve a one-clock-wide pulse, but not at an arbitrary time within the ARR cycle.

JW