2016-08-05 10:36 AM
Hi.
Is it possible to achieve that combination somehow? I am using F303 which has max. SYSCLK 72 MHz (this could go lower). But I would need one timer which runs at 6 MHz and SPI CLK with 8 MHz.2016-08-05 11:09 AM
SPI is the main constraint, the divisors of which are powers of 2, thus the only clock yielding 8MHz is 64MHz (maybe also 32MHz, I am not much into the F3s), and you can't achieve 6MHz dividing that.
There is a way around though, generating 8MHz from 72MHz in an other timer, and then feeding it into SPI running as slave externally. JW2016-08-05 11:25 AM
Hi Jan.
Could you explain please a little bit more, how do you mean to generate 8 MHz clock for SPI with another timer? I understand that Timer could run at 8 MHz with prescaler 8, if SYSCLK is 72 MHz. (72 / (8+1)) But how could I feed that to SPI?Thanks a lot2016-08-05 11:33 AM
SPI can be slaved
If I wanted a 6 MHz clock, I'd use a 6 or 12 MHz HSE crystal and push that out PA8 MCO pin. Pretty sure you could then play games with the PLL (multipliers/dividers) to get to 64 MHz so you could get to 8 MHz on one of the SPI peripherals.2016-08-05 01:25 PM
> But how could I feed that to SPI?
As I said above, externally. I mean, output the 8MHz through a CC channel onto a pin, and connect that pin with the SCK pin of the SPI. JW