Timer 15 encoder mode !

[shingadaddy]

Posted on August 23, 2016 at 22:41

Yeah well I'm going to say that even though the input sections of timer 15 *seem* to have the necessary signaling input conditioning (xor)  so it could be used as a quadrature encoder signal interface, it seems odd that the SMCR doesn't offer ENCODER mode for this counter.

So NO ENCODER MODE on timer 15. Right? 

#timer-15-encoder-mode

[Tesla DeLorean]

Posted on August 23, 2016 at 22:51

On what part? The Reference Manual typically covers what functionality specific groups of TIMs support.

[shingadaddy]

Posted on August 23, 2016 at 23:02 STM32L476

Data sheet and user manual seem to not mention encoder for that timer but sure looks like it would do it. I honestly thought I saw talk on here about this very thing but my searches didn't produce anything about it. Well THIS time anyway.. :\ Of course

Now that I've said ''I can't find it'' I have given the go ahead to apply the usual embarrassment on me. Maximizing my chances of using it as another encoder input.

[shingadaddy]

Posted on August 23, 2016 at 23:10

User manual does have interesting reading though. How DO you set the binary value of bit 2-0 to 1000

@@

   >

-

Bits 2:0

SMS:

Slave mode selection

When external signals are selected the active edge of the trigger signal (TRGI) is linked to the

polarity selected on the external input (see Input Control register and Control Register

description.

0000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal

clock.

0001: Reserved

0010: Reserved

0011: Reserved

0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter

and generates an update of the registers.

0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The

counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of

the counter are controlled.

0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not

reset). Only the start of the counter is controlled.

0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.

1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)

reinitializes the counter, generates an update of the registers and starts the counter.

Other codes: reserved.

Note: The gated mode must not be used if TI1F_ED is selected as the trigger input

(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the

gated mode checks the level of the trigger signal.

Note: The clock of the slave timer must be enabled prior to receive events from the master

timer, and must not be changed on-the-fly while triggers are received from the master

timer.

[Tesla DeLorean]

Posted on August 23, 2016 at 23:22

The RM says TIM15 is an ''upcounter'' which would seem to discount its ability to do encoder work, although the block diagram seems to suggest otherwise. I think the diagram overstates the functionality. Will push to moderation.

''TIM15 includes the following features:• 16-bit auto-reload upcounter'' vs ''Figure 298. TIM15 block diagram''

http://www.st.com/content/ccc/resource/technical/document/reference_manual/02/35/09/0c/4f/f7/40/03/DM00083560.pdf/files/DM00083560.pdf/jcr:content/translations/en.DM00083560.pdf

[shingadaddy]

Posted on August 23, 2016 at 23:32

Datasheet DocID025976 Rev 4 shows it as UPCOUNT only also.

Not sure what to make of it. Might set the bits and give it a try but that 1000 value still eludes me.

Thanks clive1

[shingadaddy]

Posted on August 23, 2016 at 23:55

And the data sheet doc and ref manual both have the same *4 bits explanation (1000) in a 3 bit field* oddity also. Might want to let them know about that too.

[waclawek.jan]

Posted on August 24, 2016 at 09:58

- the XOR is not a prerequisite of encoder mode

- SMS[3] is bit 16 of SMCR (might have been a note at the description) JW

[shingadaddy]

Posted on August 24, 2016 at 16:21

Thanks JW-

Well okay - but - REF Manual 351

26.3.25 Interfacing with Hall sensors

This is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to drive the motor and another timer TIMx (TIM2, TIM3, TIM4) referred to as “interfacing timer�in Figure 244. The “interfacing timer� captures the 3 timer input pins (CC1, CC2, CC3) connected through a XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register).

I read that and thought it (xor) was important so my brain associated ''encoder/xor'' relationship.

Yeah that SMS(3) thing..... Seem the SMCR registers are alike that.The folks allocating bits in the registers had to deal with what looks to be an AFTERTHOUGHT for a 4th bit needed by the SMS folks. The OCCS bit must have already been glued down in the silicon.