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Tamper Detection Behavior During VDD Shutdown (VBAT = 1.55V)

ZHIYAR-TAHIR
Associate

Hello Experts,

I am using the STM32L476QEI6 in one of my projects. The system VDD is 3.3V, and VBAT is supplied by a 1.55V coin cell battery (Murata SR621SW).

The tamper pin (PC13) is connected to an anti-tamper switch normally closed (NC) — meaning the switch is open only when the box is closed. I’ve configured the tamper detection in level detection mode, using:

  • Sampling frequency: 1 Hz

  • Precharge duration: 8 cycles

  • External capacitor: 2.2 nF (C0G) 

  • Tamper is triggered on low level

What I’m concerned about is the behavior on 

 

RTC when VDD is shut down — for example, due to a power failure or brownout. Let's say I’ve configured the BOR level 4,

So, when the RTC switches from VDD to VBAT (1.55V), is there a risk of a false tamper detection being triggered due to the voltage transition?

Best regards,

ZHIYAR TAHIR

Screenshot_1.png

 

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